6
Switching Specifications
Over recommended temperature (T
A
= 0°C to 70°C), V
CC
= 5 V, unless otherwise specified.
Sym- Device
Parameter bol HCPL- Min. Typ.* Max. Unit Test Conditions Fig. Note
Propagation t
PHL
M701 25 75 µsT
A
= 25°CI
F
= 0.5 mA, 5, 6,
100 7
0.5 2 T
A
= 25°CI
F
= 12 mA,
3
M700 5 20 T
A
= 25°CI
F
= 1.6 mA,
25
Propagation t
PLH
M701 10 60 T
A
= 25°CI
F
= 0.5 mA, 5, 6,
90 7
110 T
A
= 25°CI
F
= 12 mA,
15
M700 10 35 T
A
= 25°CI
F
= 1.6 mA,
50
Common |CM
H
| 1,000 10,000 V/µsI
F
= 0 mA 8 4, 5
Mode R
L
= 2.2 kΩ
Transient |V
CM
| = 10 V
p-p
Immunity at
Logic High
Output
Common |CM
L
| 1,000 10,000 V/µsI
F
= 1.6 mA 8 4, 5
Mode R
L
= 2.2 kΩ
Transient |V
CM
| = 10 V
p-p
Immunity at
Logic Low
Output
*All typicals at T
A
= 25°C.
R
L
= 4.7 kΩ
R
L
= 270 Ω
R
L
= 2.2 kΩ
R
L
= 4.7 kΩ
R
L
= 270 Ω
R
L
= 2.2 kΩ
Notes:
1. dc CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, I
O
, to the forward LED input
current, I
F
, times 100.
2. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together.
3. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second
(leakage detection current limit, I
I-O
≤ 5 µA).
4. Common transient immunity in a Logic High level is the maximum tolerable (positive) dV
CM
/dt on the rising edge of the
common mode pulse, V
CM
, to assure that the output will remain in a Logic High state (i.e., V
O
> 2.0 V). Common mode transient
immunity in a Logic Low level is the maximum tolerable (negative) dV
CM
/dt on the falling edge of the common mode pulse
signal, V
CM
, to assure that the output will remain in a Logic Low state (i.e., V
O
< 0.8 V).
5. In applications where dV/dt may exceed 50,000 V/µs (such as static discharge) a series resistor, R
CC
, should be included to
protect the detector IC from destructively high surge currents. The recommended value is R
CC
= 220 Ω.
6. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
Delay Time
to Logic
Low at
Output
Delay Time
to Logic
High at
Output
