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ICS932S801AGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
10
ICS932S801
0959C—03/13/06
General SMBus serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
11
ICS932S801
0959C—03/13/06
SMBus Table: Frequency Select and Spread Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
FS Source
Latched Input or SMBus
Frequency Select
RW
Latched
Inputs
SMBus 0
Bit 6
CPU SS_EN RW OFF ON 0
Bit 5
SRC SS_EN RW OFF ON 0
Bit 4
Reserved Reserved RW Reserved Reserved 0
Bit 3
FS3 Freq Select Bit 3 RW 0
Bit 2
FS2 Freq Select Bit 2 RW Latched
Bit 1
FS1 Freq Select Bit 1 RW Latched
Bit 0
FS0 Freq Select Bit 0 RW Latched
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
PCICLK3 Output Enable RW Disable (Low) Enable 1
Bit 6
PCICLK2 Output Enable RW Disable (Low) Enable 1
Bit 5
PCICLK1 Output Enable RW Disable (Low) Enable 1
Bit 4
PCICLK0 Output Enable RW Disable (Low) Enable 1
Bit 3
HTTCLK3 Output Enable RW Disable (Low) Enable 1
Bit 2
HTTCLK2 Output Enable RW Disable (Low) Enable 1
Bit 1
HTTCLK1 Output Enable RW Disable (Low) Enable 1
Bit 0
HTTCLK0 Output Enable RW Disable (Low) Enable 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1PWD
Bit 7
48MHz_1 Output Enable RW Disable (Low) Enable 1
Bit 6
48MHz_0 Output Enable RW Disable (Low) Enable 1
Bit 5
REF1 Output Enable RW Disable (Low) Enable 1
Bit 4
REF0 Output Enable RW Disable (Low) Enable 1
Bit 3
CPUCLK8(3) R
W
Disable Enable 1
Bit 2
CPUCLK8(2) R
W
Disable Enable 1
Bit 1
CPUCLK8(1) R
W
Disable Enable 1
Bit 0
CPUCLK8(0) RW Disable Enable 1
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
-
-
-
-
-
B
y
te 1
Spread Enable for CPU
and SRC PLLs.
Setting
SPREAD_EN to '1',
forces Spread ON for
both PLLs.
B
y
te 0
-
-
-
B
y
te 2
See Functionality Table on
Page 1
12
ICS932S801
0959C—03/13/06
SMBus Table: SRCCLK(0) Output Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 Reserved Reserved RW Reserved Reserved 0
Bit 2 Reserved Reserved RW Reserved Reserved 0
Bit 1 SRCCLK0 PD
SRCCLK Power Down
Drive Mode
RW Driven Hi-Z 0
Bit 0 SRCCLK0 Output Enable RW Disable (Hi-Z) Enable 1
SMBus Table: 48MHz Drive Strength Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 Reserved Reserved RW Reserved Reserved 0
Bit 2 Reserved Reserved RW Reserved Reserved 0
Bit 1 48MHz_1 DS Drive Stren
g
th Control RW 1X 2X 0
Bit 0 48MHz_0 DS Drive Strength Control RW 1X 2X 0
SMBus Table: SRC Frequency Select Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 Reserved Reserved RW Reserved Reserved 0
Bit 6 Reserved Reserved RW Reserved Reserved 0
Bit 5 Reserved Reserved RW Reserved Reserved 0
Bit 4 Reserved Reserved RW Reserved Reserved 0
Bit 3 SRCFS1 SRC FS bit 1 RW 0
Bit 2 SRCFS0 SRC FS bit 0 RW 0
Bit 1 Reserved Reserved RW Reserved Reserved 0
Bit 0 Reserved Reserved RW Reserved Reserved 0
SMBus Table: Device ID Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 DevID 7 Device ID MSB R - - 1
Bit 6 DevID 6 Device ID 6 R - - 0
Bit 5 DevID 5 Device ID 5 R - - 0
Bit 4 DevID 4 Device ID4 R - - 0
Bit 3 DevID 3 Device ID3 R - - 0
Bit 2 DevID 2 Device ID2 R - - 0
Bit 1 DevID 1 Device ID1 R - - 0
Bit 0 DevID 0 Device ID LSB R - - 1
-
-
-
-
-
See Table 1:
SRC Frequency Select
Byte 5
-
-
-
-
5
4
Byte 6
-
-
-
-
-
-
-
-
Byte 4
-
-
-
-
Byte 3
-
-
-
-
-
-
-
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ICS932S801AGLF

Mfr. #:
Buy ICS932S801AGLF
Manufacturer:
Description:
IC K8 CLOCK CHIP 48-TSSOP
Lifecycle:
New from this manufacturer.
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