ICS932S801AGLF Datasheet 932S801AFLF, ICS932S801AFLFT, ICS932S801AGLFT | P19-P20

ICS932S801

0959C—03/13/06

Ordering Information

ICS932S801yGLFT

Example:

Designation for tape and reel packaging

RoHS Compliant

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS XXXX y G - LF T

INDEX

AREA

INDEX

AREA

1 2

SEATING

PLANE

SEATING

PLANE

- C -

aaa

MIN MAX MIN MAX

A -- 1.20 -- .047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.17 0.27 .007 .011

c 0.09 0.20 .0035 .008

E1 6.00 6.20 .236 .244

L 0.45 0.75 .018 .030

a0°8°0°8°

aaa -- 0.10 -- .004

VARIATIONS

MIN MAX MIN MAX

48 12.40 12.60 .488 .496

10-0039

D mm. D (inch)

Reference Doc.: JEDEC Publication 95, MO-153

0.50 BASIC 0.020 BASIC

SEE VARIATIONS SEE VARIATIONS

8.10 BASIC 0.319 BASIC

(240 mil) (20 mil)

SYMBOL

In Millimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

ICS932S801

0959C—03/13/06

Revision History

Rev. Issue Date Description Page #

B 5/18/2005

1. Updated Electrical Characteristics Tables:

i) Changed SRC jitter from 125ps to 100ps;

ii) Changed PCI/HTT Skew from 500ps to 200ps;

iii) Added USB Skew, 50ps.

iv) Change REF Skew from 500ps to 50ps.

2. Updated LF Orderin

Information from "Lead Free" to "RoHS Compliant".

14-16

18-19

C 3/13/2006

1. Correct pin description of PD# (Pin 21). It does not contain a pull up resistor.

2. Added PCIe Gen 1 phase noise numbers to SRC output characterisitics 2, 7

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

ICS932S801AGLF

Mfr. #:

Buy ICS932S801AGLF

Manufacturer:

Description:

IC K8 CLOCK CHIP 48-TSSOP

Lifecycle:

New from this manufacturer.

Delivery:

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ICS932S801AGLF

ICS932S801AGLF

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