ISL6269B
13
FN6280.3
November 17, 2014
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Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 5
is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is
adjusted for converter efficiency. The ripple current calculation is
written as shown in Equation 14
:
Where:
-I
MAX
is the maximum continuous I
LOAD
of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage of
I
MAX
(0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as shown in
Equation 15
:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum V
DS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that the
device spends the least amount of time dissipating power in the
linear region. Unlike the low-side MOSFET, which has the drain to
source voltage clamped by its body diode during turn off, the
high-side MOSFET turns off with V
IN
-V
OUT
-V
L
across it. The
preferred low-side MOSFET emphasizes low r
DS(ON)
when fully
saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as:
For the high-side MOSFET, (HS), its conduction loss is written as:
For the high-side MOSFET, its switching loss is written as:
Where:
-I
VALLEY
is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
-I
PEAK
is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
-t
ON
is the time required to drive the device into saturation
-t
OFF
is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Where:
-Q
g
is the total gate charge required to turn on the high-side
MOSFET
- V
BOOT
, is the maximum allowed voltage decay across the
boot capacitor each time the high-side MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total gate
charge Q
g
, of 25nC at V
GS
= 5V and a V
BOOT
of 200mV. The
calculated bootstrap capacitance is 0.125µF. For a comfortable
margin select a capacitor that is double the calculated
capacitance, in this example 0.22µF will suffice. Use an X7R or
X5R ceramic capacitor.
(EQ. 14)
I
IN_RMS
I
MAX
2
DD
2
xI
MAX
2
D
12
------



+
I
MAX
-----------------------------------------------------------------------------------------------------
=
D
V
OUT
V
IN
EFF
--------------------------
=
(EQ. 15)
ISL6269B
14
FN6280.3
November 17, 2014
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Layout Considerations
As a general rule, power should be on the bottom layer of the
PCB and weak analog or logic signals are on the top layer of the
PCB. The ground-plane layer should be adjacent to the top layer
to provide shielding. The ground plane layer should have an
island located under the IC, the compensation components and
the FSET components. The island should be connected to the rest
of the ground plane layer at one point.
Signal Ground and Power Ground
The bottom of the ISL6269B QFN package is the signal ground
(GND) terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL6269B to the island of ground plane under the
top layer using several vias, for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors and the source of the lower MOSFETs to the power
ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to the
source of the low-side MOSFET with a low resistance, low
inductance path.
VIN (PIN 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low inductance
path.
VCC (PIN 2)
For best performance, place the decoupling capacitor very close
to the VCC and GND pins.
PVCC (PIN 12)
For best performance, place the decoupling capacitor very close
to the PVCC and PGND pins, preferably on the same side of the
PCB as the ISL6269B IC.
FCCM (PIN 3), EN (PIN 4), PGOOD (PIN 16)
These are logic inputs that are referenced to the GND pin. Treat
as a typical logic signal.
COMP (PIN 5), FB (PIN 6) AND VO (PIN 8)
For best results, use an isolated sense line from the output load
to the VO pin. The input impedance of the FB pin is high, so place
the voltage programming and loop compensation components
close to the VO, FB and GND pins keeping the high impedance
trace short.
FSET (PIN 7)
This pin requires a quiet environment. The resistor R
FSET
and
capacitor C
FSET
should be placed directly adjacent to this pin.
Keep fast moving nodes away from this pin.
ISEN (PIN 9)
Route the connection to the ISEN pin away from the traces and
components connected to the FB pin, COMP pin and FSET pin.
LG (PIN 11)
The signal going through this trace is both high dv/dt and high
di/dt with high peak charging and discharging current. Route this
trace in parallel with the trace from the PGND pin. These two
traces should be short, wide and away from other traces. There
should be no other weak signal traces in proximity with these
traces on any layer.
BOOT (PIN 13), UG (PIN 14), PHASE (PIN 15)
The signals going through these traces are both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route the UG and PHASE pins in parallel with short and wide
traces. There should be no other weak signal traces in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase
node should be kept very low to minimize ringing. It is best to
limit the size of the PHASE node copper in strict accordance with
the current and thermal management of the application. An
MLCC should be connected directly across the drain of the upper
MOSFET and the source of the lower MOSFET to suppress the
turn-off voltage spike.
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
HIGH-SIDE
MOSFETS
ISL6269B
15
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6280.3
November 17, 2014
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About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
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.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
November 17, 2014 FN6280.3 -Updated Template.
-Updated intersil trademark statement at the bottom of page one.
-Ordering information table on page 2, updated Note 1 from "*Add"-T" suffix for tape and reel" to “Add “-T*”
suffix for tape and reel. Please refer to TB347 for details on reel specifications."
-Ordering information table on page 2: Added MSL Note 3.
-On page 6, updated Caution statement per legal's new verbiage.
-On page 8, updated Note 6 from "Guaranteed by characterization." to "Compliance to limits is assured by
characterization and design."
-Added revision history and about Intersil verbiage.
-Updated L16.4x4 to new POD format by removing table listing dimensions and moving dimensions onto
drawing.
-Added Typical Recommended Land Pattern.

ISL6269BCRZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers GPU CNTRLR 16LD 4X4
Lifecycle:
New from this manufacturer.
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