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CSPU877ABVG

P1-P3P4-P6P7-P9P10-P12P13-P13
7
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUIT AND SWITCHING WAVEFORMS
Figure 1: Output Load Test Circuit 1
Figure 2: Output Load Test Circuit 2
VDDQ
CSPU877A
GND
R=120Ω
Z=60Ω
Z=60Ω
C = 10pF
C = 10pF
GND
GND
SCOPE
L=2.97"
L=2.97"
R=1MΩ
C = 1pF
0V
R=1MΩ
C = 1pF
0V
VDDQ/2
VDDQ/2
R=10Ω
Z=60Ω
Z=60Ω
C = 10pF
C = 10pF
Z=50Ω
Z=50Ω
R=50Ω
R=50Ω
R=10Ω
SCOPE
CSPU877A
V
DDQ/2
VDDQ/2
L=2.97"
L=2.97"
V
TT
VTT
NOTE: VTT =GND
8
COMMERCIAL TEMPERATURE RANGE
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
(N is a large number of samples)
Cycle-to-Cycle jitter
Static Phase Offset
Output Skew
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT
tjit(cc) tcycle n tcycle n+1
=
Yx, FBOUT
tcycle n tcycle n+1
FBIN
CLK
t(Ø)n
t(Ø)n + 1
t(Ø)
=
N
n=N
1
t(Ø)n
∑
CLK
FBIN
Yx, FBOUT
Yx
tsk(o)
Yx, FBOUT
Yx
9
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
Period jitter
Half-Period jitter
TEST CIRCUIT AND SWITCHING WAVEFORMS
NOTE:
fo = Average input frequency measured at CLK / CLK
NOTE:
fo = Average input frequency measured at CLK / CLK
Yx, FBOUT
Yx, FBOUT
tjit(per)
=
tcycle n
1
f
o
Yx, FBOUT
Yx, FBOUT
tcycle n
1
f
o
Yx, FBOUT
Yx, FBOUT
1
f
o
tjit(hper)
=
thalf period n
1
2*f
o
Yx, FBOUT
Yx, FBOUT
thalf period n
thalf period n+1
P1-P3P4-P6P7-P9P10-P12P13-P13

CSPU877ABVG

Mfr. #:
Buy CSPU877ABVG
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1.8V PLL Differ 1:10 DDR 2 Clock Driver
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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