NCP1361, NCP1366
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16
APPLICATION INFORMATION
The NCP1366/61 is a flyback power supply controller
providing a means to implement primary side
constant−current regulation. This technique does not need a
secondary side feedback circuitry, associated bias current
and an opto−coupler. NCP1366/61 implements a
current−mode architecture operating in quasi−resonant
mode. The controller prevents valley−jumping instability
and steadily locks out in a selected valley as the power
demand goes down. As long as the controller is able to detect
a valley, the new cycle or the following drive remains in a
valley. Due to a dedicated valley detection circuitry
operating at any line and load conditions, the power supply
efficiency will always be optimized. In order to prevent any
high switching frequency two frequency clamp options are
available.
Quasi−Resonance Current−mode operation:
implementing quasi−resonance operation in peak
current−mode control optimizes the efficiency by
switching in the valley of the MOSFET drain−source
voltage. Due to a proprietary circuitry, the controller
locks−out in a selected valley and remains locked until
the input voltage significantly changes. Only the four
first valleys could be locked out. When the load current
diminishes, valley switching mode of operation is kept
but without valley lock−out. Valley−switching
operation across the entire input/output conditions
brings efficiency improvement and lets the designer
build higher−density converters.
Frequency Clamp: As the frequency is not fixed and
dependent on the line, load and transformer
specifications, it is important to prevent switching
frequency runaway for applications requiring maximum
switching frequencies up to 90 kHz or 130 kHz. Two
frequency clamp options at 80 kHz or 110 kHz are
available for this purpose. In case frequency clamp is
not needed, a specific version of the 1361/66 exists in
which the clamp is deactivated.
Primary Side Constant Current Regulation: Battery
charging applications request constant current
regulation. NCP1361/66 controls and regulates the
output current at a constant level regardless of the input
and output voltage conditions. This function offers tight
over power protection by estimating and limiting the
maximum output current from the primary side, without
any particular sensor.
Optocoupler−based feedback: the voltage feedback
loop is classically implemented with an optocoupler
and a NCP431 voltage reference in the secondary side.
By pulling the feedback pin low, the controller adjusts
the peak current setpoint and regulates V
out
.
V
out
I
out
Optocoupler−based feedback
CC mode
0
V
nom
I
nom
Figure 39. Constant−Voltage & Constant−Current
Mode
Primary−side
Soft−Start: 4 ms internal fixed soft start guarantees a
peak current starting from zero to its nominal value
with smooth transition in order to prevent any
overstress on the power components at each startup.
Cycle−by−Cycle peak current limit: If the max peak
current reaches the V
ILIM
level, the over current
protection timer is enabled and starts counting. If the
overload lasts T
OCP
delay, then the fault is latched and
the controller stops immediately driving the power
MOSFET. The controller enters in a double hiccup
mode before autorecovering with a new startup cycle.
V
CC
Over Voltage Protection: If the V
CC
voltage
reaches the V
CC(OVP)
threshold the controller enters in
latch mode. Thus it stops driving pulse on DRV pin:
A & C version − (Latched V
CC(OVP)
): V
CC
capacitor is internally discharged to the V
CC(Clamp)
level with a very low power consumption: the
controller is completely disabled. Resuming
operation is possible by unplugging the line in order
to releasing the internal V
CC
thyristor with a V
CC
current lower than the I
CC(Clamp)
.
B version − (Autorecovery): it enters in double
hiccup mode before resuming operation.
Winding Short−Circuit Protection: An additional
comparator senses the CS signal and stops the
controller if V
CS
reaches V
ILIM
+50% (after a reduced
LEB: t
LEB2
). Short circuit protection is enabled only if
4 consecutive pulses reach SCP level. This small
counter prevents any false triggering of short circuit
protection during surge test for instance. This fault is
latched and operations will be resumed like in a case of
V
CC
Over Voltage Protection.
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17
V
out
Over Voltage Protection: if the internally−built
output voltage becomes higher than V
OVP
level
(V
ref_CV1
+ 26%) a fault is detected.
A & C version: This fault is latched and operations
are resumed like in the V
CC
Over Voltage Protection
case.
B version: the part enters in double hiccup mode
before resuming operations.
V
out
Under Voltage Protection: After each circuit
power on sequence, V
out
UVP detection is enabled only
after the startup timer T
EN_UVP
. This timer ensures that
the power supply is able to fuel the output capacitor
before checking the output voltage in on target. After
this startup blanking time, UVP detection is enabled
and monitors the Output voltage level. When the power
supply is running in constant−current mode and when
the output voltage falls below V
UVP
level, the controller
stops sending drive pulses and enters a double hiccup
mode before resuming operations (A & B version), or
latches off (C version).
V
s
/ZCD Pin Short Protection: at the beginning of
each off−time period, the V
s
/ZCD pin is tested to check
whether it is shorted or left open. In case a fault is
detected, the controller enters in a double hiccup mode
before resuming operations.
Temperature Shutdown: if the junction temperature
reaches the T
SHTDN
level, the controller stop driving the
power mosfet until the junction temperature decreases
by T
SHTDN(HYS)
, then the operation is resumed after a
double hiccup mode.
Startup Operation
The high−voltage startup current source is connected to
the bulk capacitor via the HV pin, it charges the V
CC
capacitor. During startup phase, it delivers 100 mA to fuel the
V
CC
capacitor. When V
CC
pin reaches V
CC(on)
level, the
NCP1361/66 is enabled. Before sending the first drive pulse
to the power MOSFET, the CS pin has been tested for an
open or shorted situation. If CS pin is properly wired, then
the controller sends the first drive pulse to the power
MOSFET. After sending these first pulses, the controller
checks the correct Vs/ZCD pin wiring. Considering the
Vs/ZCD pin properly wired, the controller engages a
softstart sequence. The softstart sequence controls the max
peak current from the minimal frozen primary peak current
(V
CS(VCO)
= 120 mV: 15% of V
ILIM
) to the nominal pulse
width by smoothly increasing the level.
Figure 40 illustrates a standard connection of the HV pin
to the bulk capacitor. If the controller is in a latched fault
mode (ex V
CC_OVP
has been detected), the power supply will
resume the operation after unplugging the converter from
the ac line outlet. Due the extremely low controller
consumption in latched mode, the release of the latch could
be very long. The unplug duration for releasing the latch will
be dependent on the bulk capacitor size.
L
N
8
5DRV GND
Vs/ZCD
HV
FB
6VccCS
V
bulk
R
HV
C
Vcc
V
aux
1
2
4
2
Figure 40. HV Startup Connection to the Bulk Capacitor (NCP1366)
The following calculation illustrates the time needed for
releasing the latch state:
t
unplug
u
C
bulk
V
in_ac
2
Ǹ
I
HV
(eq. 1)
For the following typical application with a 10 mF bulk
capacitor and a wide mains input range, in the worst case the
power supply needs to be unplug at least for 38 seconds @
265 V ac and 12 seconds @ 85 Vac. It is important to note
that the previous recommendation is no longer valid with the
B version, as all the faults are set to autorecovery mode only.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designers duty to avoid the presence of negative
spikes on sensitive pins. Negative injection has the bad habit
to forward−bias the controller substrate and can induce
erratic behaviors. Sometimes, the injection can be so strong
that internal parasitic SCRs are triggered and latch the
controller. The HV pin can be the problem in certain
circumstances. During the turn−off sequence, e.g. when the
user unplugs the power supply, the controller is still fed by
its V
CC
capacitor and keeps activating the MOSFET ON and
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18
OFF with a peak current limited by R
sense
. Unfortunately, if
the quality factor Q of the resonating network formed by L
p
and C
bulk
is high (e.g. the MOSFET R
DS(on)
+ R
sense
are
small), conditions are met to make the circuit resonate and
a negative ringing can potentially appear at the HV pin.
Simple and inexpensive cures exist to prevent the internal
parasitic SCR activation. One of them consist of inserting a
resistor in series with the HV pin to keep the negative current
at the lowest when the bulk swings negative (Figure 40).
Another option (Figure 41) consists of connecting the
HV pin directly to the line or neutral input via a high−voltage
diode. This configuration offers the benefits to release a
latch state immediately after unplugging the power supply
from the mains outlet. There is no delay for resetting the
controller as there no capacitor keeps the HV bias.
R
HV
resistor value must be sized as follow in order to
guarantee a correct behavior of the HV startup in the worst
case conditions:
R
HV
t
V
in,ac_min
2
Ǹ
* V
HV(min)_max
I
HV_max
(eq. 2)
Where:
V
in,ac_min
is minimal input voltage, for example 85 V ac
for universal input mains.
V
HV(min)_max
is the worst case of the minimal input
voltage needed for the HV startup current source
(25 V−max).
I
HV_max
is the maximum current delivered by the HV
startup current source (150 mA−max)
With this typical example
R
HV
t
85 2
Ǹ
* 25
150 m
+ 633 kW,
then any value below this one will be ok.
L
N
1
2
4
8
5DRV GND
Vs/ZCD
HV
FB
6VCC2CS
V
bulk
V
aux
C
Vcc
Figure 41. Recommended HV Startup Connection for Fast Release after a Latched Fault (NCP1366)
Primary Side Regulation: Constant Current Operation
Figure 42 portrays idealized primary and secondary
transformer currents of a flyback converter operating in
Discontinuous Conduction Mode (DCM).
Figure 42. Primary and Secondary Transformer Current Waveforms
I
p
(t)
I
s
(t), I
OUT
I
OUT
= <I
s
(t)
>
,
,
ppk
spk
I
ps
I
N
=
,p
I
pk
t
demag
t
sw
time
time
t
on

NCP1361EABAYSNT1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers LOW POWER OFFLINE CO
Lifecycle:
New from this manufacturer.
Delivery:
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