NCP1361, NCP1366
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23
This ensures the MOSFET current setpoint remains
limited to V
ILIM
in a fault condition.
FB Reset
Max_Ipk reset
OCP
Timer
Count
Reset Timer
LEB1
CS
V
ILIM
POReset
DbleHiccup
LEB2
V
CS(Stop)
4 clk
Counter
Reset
Counter
OCP
1/K
comp
SCP
Peak current
Freeze
Control Law
For
Primary Peak
Current Control
SoftStart
FB_CV
FB_CC
PWM
Latch
Reset
PWM Comp
OCP
Comp
Short Circuit
Comp
R
sense
R
CS
C
CS
Figure 47. Current Setpoint
A 2nd Over−Current Comparator for Abnormal
Overcurrent Fault Detection
A severe fault like a winding short−circuit can cause the
switch current to increase very rapidly during the on−time.
The current sense signal significantly exceeds V
ILIM
. But,
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can abnormally increase, possibly causing system damages.
The NCP1361/66 protects against this dangerous mode by
adding an additional comparator for abnormal overcurrent
fault detection or short−circuit condition. The current sense
signal is blanked with a shorter LEB duration, t
LEB2
,
typically 120 ns, before applying it to the short−circuit
comparator. The voltage threshold of this extra comparator,
V
CS(stop)
, is typically 1.2 V, set 50% higher than V
ILIM
. This
is to avoid interference with normal operation. Four
consecutive abnormal overcurrent faults cause the
controller to enter in auto−recovery mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
fault overcurrent comparator or after double hiccup
sequence or if the power supply is unplugged with a new
startup sequence after the initial power on reset.
Standby Power Optimization
Assuming the no−load standby power is a critical
parameter, the NCP1361/66 is optimized to reach an ultra
low standby power. When the controller enters standby
mode, a part of the internal circuitry has been disabled in
order to minimize its supply current. When the STBY mode
is enabled, the consumption is only 200 mA (I
CC4
) with the
200 Hz minimal frequency option.
Fault mode and Protection
♦ CS pin: at each startup, a 55 mA (I
CS
) current source
pulls up the CS pin to disable the controller if the pin
is left open or grounded. Then the controller enters
in a double hiccup mode.
♦ Vs/ZCD pin: after sending the first drive pulse the
controller checks the correct wiring of Vs/ZCD pin:
after the ZCD blanking time, if there is an open or
short conditions, the controller enters in double
hiccup mode.
Thermal Shutdown: An internal thermal shutdown circuit
monitors the junction temperature of the IC. The controller
is disabled if the junction temperature exceeds the thermal
shutdown threshold (T
SHDN
), typically 150°C. A continuous
V
CC
hiccup is initiated after a thermal shutdown fault is
detected. The controller restarts at the next V
CC(on)
once the
IC temperature drops below T
SHDN
reduced by the thermal
shutdown hysteresis (T
SHDN(HYS)
), typically 40°C. The
thermal shutdown is also cleared if V
CC
drops below
V
CC(reset)
. A new power up sequences commences at the
next V
CC(on)
once all the faults are removed.
Driver
The NCP1361/66 maximum supply voltage, V
CC(max)
, is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp which limits the gate voltage on the
external mosfet. The DRV voltage clamp, V
DRV(high)
is set to
13 V maximum.
