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MAX807LCWE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
10 ______________________________________________________________________________________
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. WDO goes
low if no transition occurs at WDI during the watchdog-
timeout period. The watchdog function is disabled and
WDO is a logic high when V
CC
is below the reset
threshold or WDI is an open circuit. To generate a sys-
tem reset on every watchdog fault, diode-OR connect
WDO to MR (Figure 6). When a watchdog fault occurs
in this mode, WDO goes low, which pulls MR low, caus-
ing a reset pulse to be issued. As soon as reset is
asserted, the watchdog timer clears and WDO returns
high. With WDO connected to MR, a continuous high or
low on WDI will cause 200ms reset pulses to be issued
every 1.6s.
Chip-Enable Signal Gating
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
The 8ns (max) chip-enable propagation from CE IN to
CE OUT enables the MAX807 to be used with most µPs.
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
is asserted. During a power-down sequence when V
CC
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28µs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
In the high-impedance mode, the leakage currents into
this input are ±1µA (max) over temperature. In the low-
impedance mode, the impedance of CE IN appears as
a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
MR
RESET
CE IN
0V
170ns
28µs TYP
1µs MIN
CE OUT
V
CC
V
RST
RESET
t
WD
WDO
WDI
WDO CONNECTED TO µP INTERRUPT.
t
RP
Figure 4. Manual-Reset Timing Diagram
Figure 5. Watchdog Timing Relationship
V
CC
V
CC
RESET
WDO
WDO
4.7kΩ
TO µP
MR
RESET
WDI
t
RP
t
RP
t
WD
∼50µs
MAX807
Figure 6. Generating a Reset on Each Watchdog Fault
MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________ 11
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
OUT is actively pulled to the higher of V
CC
or V
BATT
. This
source turns off when the transmission gate is enabled.
Low-Line Comparator
The low-line comparator monitors V
CC
with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
maskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system must
contend with a more rapid V
CC
fall time—such as when
the main battery is disconnected, a DC-DC converter
shuts down, or a high-side switch is opened during
normal operation—use capacitance on the V
CC
line to
provide time to execute the shutdown routine (Figure 9).
First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (V
LR(min)
),
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
C
HOLD
= (I
LOAD
x t
SHDN
) / V
LR
(min)
where t
SHDN
is the time required for the system to com-
plete the shutdown routine, and includes the V
CC
to
low-line propagation delay; and where I
LOAD
is the cur-
rent being drained from the capacitor, V
LR
is the low-
line to reset threshold.
V
CC
CE IN
RESET
THRESHOLD
CE OUT
RESET
RESET
26µs
28µs
26µs
MAX807
CE IN
50pF
C
LOAD
CE OUT
GND
V
RST
MAX
50Ω DRIVER
V
CC
Figure 7. Reset and Chip-Enable Timing Figure 8. CE Propagation Delay Test Circuit
GND
V
CC
TO µP NMI
C
HOLD
C
HOLD
> I
LOAD
x t
SHDN
V
LR
4.5V to 5.5V
LOW LINE
MAX807
REGULATOR
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP
MAX807L/M/N
Power-Fail Comparator
PFI is the noninverting input to an uncommitted com-
parator. If PFI is less than V
PFT
(2.265V), PFO goes low.
The power-fail comparator is intended to monitor the
preregulated input of the power supply, providing an
early power-fail warning so software can conduct an
orderly shutdown. It can also be used to monitor sup-
plies other than 5V. Set the power-fail threshold with a
resistor-divider, as shown in Figure 10.
Power-Fail Input
PFI is the input to the power-fail comparator. The typical
comparator delay is 14µs from V
IL
to V
OL
(power failing),
and 32µs from V
IH
to V
OH
(power being restored). If
unused, connect this input to ground.
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes
below V
PFT
. It typically sinks 3.2mA with a saturation
voltage of 0.1V. With PFI above V
PFT
, PFO is actively
pulled to V
CC
. Connecting PFI through a voltage-
divider to a preregulated supply allows PFO to gener-
ate an NMI as the preregulated power begins to fall
(Figure 11b). If the preregulated supply is inaccessible,
use LOW LINE to generate the NMI (Figure 11a). The
LOW LINE threshold is typically 52mV above the reset
threshold (see the Low-Line Comparator section).
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
12 ______________________________________________________________________________________
MAX807
V
CC
GND
PFI PFO
R1
R2
V
IN
0V
V
IN
PFO
V
TRIP
V
L
V
PFT
= 2.265V
V
PFH
= 20mV
WHERE
V
TRIP
= R2
+
R1
1
)
(
R2
1
–
R1
V
CC
(V
PFT
+ V
PFH
)
V
L
= R2
+
R1
1
)
(
R2
1
–
R1
V
CC
(V
PFT
)
NOTE: V
TRIP,
V
L
ARE NEGATIVE.
V
CC
MAX807
V
CC
GND
PFI PFO
R1
R2
PFO
V
TRIP
V
H
V
IN
V
TRIP
=
)
(
R2
R1
+
R2
V
PFT
V
H
=
(V
PFT
+
V
PFH
)
V
CC
V
IN
MR
b)a)
)
(
R2
R1
+
R2
MAX807
OUTV
CC
FROM
REGULATED
SUPPLY
POWER TO
CMOS RAM
BATT
RESET
LOW LINE
WDI
GND
RESET
NMI
I/O LINE
µP
µP POWER
0.1µF
0.1µF
2.8V
a)
b)
MAX807
OUTV
CC
PFI
POWER TO
CMOS RAM
BATT
RESET
PFO
WDI
GND
VOLTAGE
REGULATOR
RESET
NMI
I/O LINE
µP
µP POWER
0.1µF
0.1µF
2.8V
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) V
IN
is Negative, b) V
IN
is Positive
Figure 11. a) If the preregulated supply is inaccessible, LOW
LINE generates the NMI for the µP. b) Use PFO to generate the
µP NMI if the preregulated supply is accessible.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX807LCWE+T

Mfr. #:
Buy MAX807LCWE+T
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Full-Featured uPower Supervisor
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