MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________________________________________________________________________________ 7
Pin Description
Active-Low Reset Output. RESET is triggered and stays low when V
CC
is below the reset threshold or
when MR is low. It remains low 200ms after V
CC
rises above the reset threshold or MR returns high.
RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates.
Valid for V
CC
≥ 1V. RESET swings between V
CC
and GND.
RESET9
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog-timeout period (t
WD
), and remains low until the next transition of WDI. WDO remains high if WDI is
unconnected. WDO is high during reset. WDO swings between V
CC
and GND. Connect WDO to MR to
generate resets during watchdog faults.
WDO10
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of V
CC
or V
BATT
, when the chip-enable gate is disabled.
CE OUT11
Chip-Enable InputCE IN12
Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to V
CC
. Connect the base of a PNP transistor or gate of a PMOS
transistor to BATT ON for I
OUT
requirements exceeding 250mA. BATT ON swings between the higher of
V
CC
and V
BATT
and GND.
BATT ON13
GroundGND5
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pullup to V
CC
. It can be
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to V
CC
, or leave uncon-
nected if not used.
MR6
Low-Line Comparator Output. This CMOS-logic output goes low when V
CC
falls to 52mV above the reset
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when V
CC
is falling.
LOW LINE swings between V
CC
and GND.
LOW LINE7
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between V
CC
and GND.
RESET8
Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO
goes low. Leave unconnected to disable the watchdog function.
WDI4
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.V
CC
3
PIN
Power-Fail Output. This CMOS-logic output goes low when PFI is less than V
PFT
(2.265V). Valid for
V
CC
≥ 4V. PFO swings between V
CC
and GND.
PFO2
Power-Fail Input. When PFI is less than V
PFT
(2.265V), PFO goes low. Connect to ground when unused.PFI1
FUNCTIONNAME
Backup-Battery Input. When V
CC
falls below the reset threshold and V
BATT
, OUT switches from V
CC
to
BATT. V
BATT
may exceed V
CC
. The battery can be removed while the MAX807 is powered-up, provided
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect V
CC
and OUT together.
BATT14
Battery-OK Signal Output. High in normal operating mode when V
BATT
exceeds V
BOK
(2.265V). Valid for
V
CC
≥ 4V.
BATT OK15
Output Supply Voltage to CMOS RAM. When V
CC
exceeds the reset threshold or V
CC
> V
BATT
, OUT is
connected to V
CC
. When V
CC
falls below the reset threshold and V
BATT
, OUT connects to BATT. Bypass
OUT with a 0.1µF capacitor to GND.
OUT16
