25
COMMERCIAL TEMPERATURE RANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 17. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3622, 512 for the IDT72V3632, 1,024 for the IDT72V3642.
Figure 18. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
AEA
CLKB
ENA
4660 drw 19
ENB
CLKA
2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
(X2+1) Words in FIFO2X2 Words in FIFO2
(1)
AFA
CLKA
ENB
4660 drw 20
ENA
CLKB
12
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)