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72V3632L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3622/72V3632/72V3642 with
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
X fo)
N
where:
N = number of outputs = 36
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010203040506070
0
25
50
75
100
125
150
V
CC
= 3.3V
f
S
Clock Frequency MHz
I
CC(f)
Supply Current mA
f
data
= 1/2 f
S
T
A
= 25
ο
C
C
L
= 0 pF
V
CC
= 3.0V
V
CC
= 3.6V
4660 drw 03a
175
200
80
90
100
8
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
IDT72V3622L10
(1)
IDT72V3622L15
IDT72V3632L10
(1)
IDT72V3632L15
IDT72V3642L10
(1)
IDT72V3642L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
tCLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3— 4—ns
tENS1 Setup Time CSA before CLKA↑; CSB before CLKB↑ 4 — 4.5 — ns
tENS2 Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB 3 — 4.5 — ns
before CLKB↑
tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ or CLKB↑
(2)
5— 5—ns
tFSS
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
7.5 — 7.5 — ns
tFWS Setup Time, FWFT before CLKA↑ 0— 0—ns
tDH
Hold Time, A0-A35 after CLKA
↑
and B0-B35 after CLKB
↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and 0.5 — 1 — ns
MBB after CLKB↑
tRSTH
Hold Time, RST1 or RST2 LOW after CLKA
↑
or CLKB
↑
(2)
4— 4—ns
tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns
tSKEW1
(3)
Skew Time, between CLKA
↑
and CLKB
↑
for EFA/ORA,
EFB/ORB, FFA/IRA, 7.5 — 7.5 — ns
and FFB/IRB
tSKEW2
(3,4)
Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 12 — 12 — ns
NOTES:
1.
For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0
°°
°°
° to +70
°°
°°
°C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING TEMPERATURE
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING TEMPERATURE, CL = 30 pF
IDT72V3622L10
(1)
IDT72V3622L15
IDT72V3632L10
(1)
IDT72V3632L15
IDT72V3642L10
(1)
IDT72V3642L15
Symbol Parameter Min. Max. Min. Max. Unit
t
A Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns
t
WEF
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFB/IRB
2 6.5 2 8 ns
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB
1 6.5 1 8 ns
t
PAE
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
1 6.5 1 8 ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
1 6.5 1 8 ns
t
PMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to 0 6.5 0 8 ns
MBF2 LOW or MBF1 HIGH
t
PMR Propagation Delay Time, CLKA↑ to B0-B35
(2)
and CLKB↑ to A0-A35
(3)
28210ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 6.5 2 10 ns
tRSF Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, 1 10 1 15 ns
and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB 2 6 2 10 ns
HIGH to B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance
and CSB HIGH or
1618ns
W/RB LOW to B0-B35 at high-impedance
NOTES:
1.
For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0
°°
°°
° to +70
°°
°°
°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

72V3632L10PF

Mfr. #:
Buy 72V3632L10PF
Manufacturer:
IDT
Description:
FIFO 512 x 36 x 2 SyncBiFIFO, 3.3V
Lifecycle:
New from this manufacturer.
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