ISL43240
9
FN6036.3
December 15, 2014
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The low leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially at
low supply voltages.
Power-Supply Considerations
The ISL43240 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and GND. V+
and V- drive the internal CMOS switches and set their analog
voltage limits, so there are no connections between the analog
signal path and GND. Unlike switches with a 13V maximum
supply voltage, the ISL43240 15V maximum supply voltage
provides plenty of room for the 10% tolerance of 12V supplies
(
6V or 12V single supply), as well as room for overshoot and
noise spikes.
This family of switches performs equally well when operated with
bipolar or single voltage supplies. The minimum recommended
supply voltage is 2V or
2V. It is important to note that the input
signal range, switching times, and on-resistance degrade at
lower supply voltages. Refer to the electrical specification tables
starting on page 3
and Typical Performance curves on page 10
for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert the
logic levels to switched V+ and V- signals to drive the analog
switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect
on logic thresholds. This switch family is TTL compatible (0.8V
and 2.4V) over a V+ supply range of 2.5V to 10V (see Figure 17
).
At 12V the V
IH
level is about 2.8V. For best results with a 12V
supply, use a logic family that provides a V
OH
greater than 3V.
The digital input stages draw supply current whenever the digital
input voltage is not at one of the supply rails (see Figure 18
).
Driving the digital input signals from GND to V+ with a fast
transition time minimizes power dissipation. The ISL43240 has
been designed to minimize the supply current whenever the
digital input voltage is not driven to the supply rails (0V to V+). For
example driving the device with 3V logic (0V to 3V) while
operating with dual or single 5V supplies the device draws only
10µA of current (see Figure 18 for V
IN
= 3V). Similar devices of
competitors can draw 8 times this amount of current.
High-Frequency Performance
In 50Ωsystems, signal response is reasonably flat even past
200MHz (see Figure 19
). Figure 19 also illustrates that the
frequency response is very consistent over a wide V+ range, and
for varying analog signal levels.
An off switch acts like a capacitor and passes higher frequencies
with less attenuation, resulting in signal feed-through from a
switch’s input to its output. Off Isolation is the resistance to this
feed-through, while Crosstalk indicates the amount of
feed-through from one switch to another. Figure 20
details the
high Off Isolation and Crosstalk rejection provided by this switch.
At 10MHz, off isolation is about 50dB in 50Ωsystems,
decreasing approximately 20dB per decade as frequency
increases. Higher load impedances decrease Off Isolation and
Crosstalk rejection due to the voltage divider action of the switch
OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One of
these diodes conducts if any analog signal exceeds V+ or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given signal pin
are identical and therefore fairly well balanced, they are reverse
biased differently. Each is biased by either V+ or V- and the
analog signal. This means their leakages will vary as the signal
varies. The difference in the two diode leakages to the V+ and V-
pins constitutes the analog-signal-path leakage current. All
analog leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is why
both sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between the
analog signal paths and GND.
FIGURE 8. OVERVOLTAGE PROTECTION
V-
V
COM
V
NO or NC
OPTIONAL PROTECTION
V+
IN
X
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
