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25
Compensation for Overpower Detection
The power delivered by a flyback power supply is
proportional to the square of the peak current:
P
OUT
+
1
2
@ h @ L
P
@ F
SW
@ I
P
2
(eq. 1)
(in discontinuous conduction mode).
Unfortunately, due to the inherent propagation delay of
the logic, the actual peak current is higher at high input
voltage than at low input voltage, as shown in Figure 50.
This leads to a significant difference in the maximum output
power delivered by the power supply.
Figure 50. Line Compensation for True Overpower Protection
time
I
P
High
Line
Low
Line
I
LIMIT
t
delay
t
delay
I
P
to be
compensated
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added to the CS signal by turning on an internal current
source (I
OPC
): by adding an external resistor (R
OPC
) in
series between the sense resistor and the CS pin, a voltage
offset is created across it by the current. The compensation
can be adjusted by changing the value of the R
OPC
resistor.
Since in light load conditions this offset is in the same
order of magnitude as the current sense signal, it must be
removed. Therefore the compensation current is only added
when the FB voltage is higher than V
FB(OPC)
, as shown in
Figure 52.
Figure 51. Schematic Overpower Compensation Circuit
HV
V to I
CS
t LEB
blanking
To CS
block
VDD
I
OPC
= 0.5m x
(VHV 125)
FB
+
+
V
FB(OPC)
HV Sensing
R
OPC
R
sense
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26
Figure 52. Overpower Compensation Current Relation to Feedback Voltage and Input Voltage
V
FB
I
OPC
V
FB(fold)
V
FB(OPC)
V
HV
A peak detector continuously senses the ac input, and its
output is periodically sampled and reset, in order to follow
closely the input voltage variations. The sample and reset
events are controlled by the brown-out comparator when the
HV pin is connected to the AC line input (as shown in Figure
53). In the case the HV pin is connected to the DC-link
capacitor, its voltage never crosses the brown-out threshold,
and the watchdog timer t
WD
is used to generate the sampling
and reset events (Figure 54). Note that depending on the
relative speeds at which the HV and VCC voltages appear at
start-up, the correct overpower compensation current may
be delayed by one cycle.
time
V
HV
time
Peak
detector
t
wd
time
I
OPC
Sample
Sample
Sample
Sample
Reset
Reset
Reset
Reset
Reset
Reset
BO threshold
Figure 53. Overpower Compensation Current with the HV pin connected to an ac voltage
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27
time
time
V
HV
Peak
detector
time
I
OPC
BO threshold
t
wd
Sample
Sample
Sample
Reset
Reset
t
wd
t
wd
t
wd
Figure 54. Overpower Compensation Current with the HV pin connected to a dc voltage
Feedback with Slope Compensation
The ratio from the FB voltage to the current sense setpoint
is typically 5. This means that the FB voltage corresponding
to V
ILIM
is 3.5 V. There is a pullup resistor of 20 kW
(typical) from FB pin to the internal reference V
FB(ref)
.
Figure 55. FB Circuitry
CS
FB
+
t LEB
blanking
VDD
Oscillator
20 kW
K
FB
slope
comp.
PWM
In order to allow the NCP1238 to operate in CCM with a
duty cycle above 50%, a fixed slope compensation is
internally applied to the currentmode control. The slope
appearing on the internal voltage setpoint for the PWM
comparator is 32.5 mV/ms typical for the 65 kHz version
(and respectively 50 mV/ms and 67 mV/ms for the
100 kHz and 133 kHz versions).

NCP1238BD65R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers DSS AUTOR SOCP 65KHZ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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