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LE25U40CQH-AH

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LE25U40CQH
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13
9. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the
timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first
bus cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase
operation starts from the rising CS
edge, and it ends automatically by the control exercised by the internal timer.
Erase end can also be detected using status register RDY
.
Figure 14 Chip Erase
10. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page
(page addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using
small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms,
and Figure 22 shows a page program flowchart. After the falling CS
, edge, the command (02H) is input followed by
the 24-bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until
the rising CS
edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes,
the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS
edge occurring at any other timing.
Figure 15 Page Program
SCK
SI
High Impedance
SO
CS
t
CHE
Self-timed
Erase Cycle
60h / C7h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
MSB
t
PP
Self-timed
Program Cycle
SCK
SI
High Impedance
SO
CS
PD
A
dd.
A
dd. 02h
A
dd. PD
15
0 1 2 3
4 5 6 7 8 2316 24 31 32 39 40 47
Mode3
Mode0
8CLK
PD
2079
MSB
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11. Silicon ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is
not accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID.
In the first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the
subsequent bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory
type, memory capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as
clock inputs are present,
"Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 16-a JEDEC ID read"
shows the JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists
the silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence
is finished by setting CS
high.
Table 7-1 JEDEC ID code Table 7-2 ID code
Output code
Output Code
Manufacturer code
62h
1 byte device ID
6E
(LE25U40C)
2 byte device ID
Memory type
06h
Memory capacity code
13h(4M Bit)
Device code 1
00h
Figure 16-a JEDEC ID Read
Figure 16-b ID Read
CS
High Impedance
13h 06h 62h
SCK
SO
SI
9Fh
15
MSB MSB MSB
0 1 2 3
4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3
32
00h
MSB
62h
MSB
CS
High Impedance
6Eh 6Eh
SCK
SO
SI
A
Bh X X
15
MSB MSB
0 1 2 3 4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3
32
X
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12. Hold Function
Using the HOLD
pin, the hold function suspends serial communication (it places it in the hold status). "Figure17
HOLD
" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD
edge. When the logic level of SCK is
high, HOLD
must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS
edge. In the hold status, the SO output is in the high-
impedance state, and SI and SCK are "don't care".
Figure 17 HOLD
13. Power-on
In order to protect against unintentional writing, CS
must be within at V
DD
0.3 to V
DD
+0.3 on power-on. After
power-on, the supply voltage has stabilized at V
DD
min. or higher, waits for t
PU
before inputting the command to
start a device operation. The device is in the standby state and not in the power-down state after power is turned on.
To put the device into the power-down state, it is necessary to enter a power-down command.
Figure 18 Power-on Timing
CS
HOLD
SCK
SO
ctive
HOLD
ctive
t
HH
t
HS
t
HLZ
t
HHZ
High Impedance
t
HH
t
HS
V
DD
(Max)
V
DD
(Min)
V
DD
0V
t
PU
CS
= V
DD
level
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LE25U40CQH-AH

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Manufacturer:
ON Semiconductor
Description:
NOR Flash FLASH MEMORY
Lifecycle:
New from this manufacturer.
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