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LE25U40CQH-AH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
LE25U40CQH
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2. Dual read
There are two Dual read commands, the Dual read command and the Dual I/O read command. They achieve the
twice speed-up from a High-speed read command.
2-1. Dual Read command
The Dual read command changes SI/SIO0 into the output pin function in addition to SO/SIO1, makes the data
output 2 bit and has achieved a high-speed output. Consisting of the first through fifth bus cycles, the Dual read
command inputs the 24-bit addresses and 8 dummy bits following (3Bh). DATA1 (Bit7, BIt5, Bit3 and Bit1) is
output from SI/SIO0 and DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of
fifth bus cycle bit 0 as a reference. "Figure 5-a Dual Read" shows the timing waveforms.
Figure 5-a Dual Read
2-2. Dual I/O Read command
The Dual I/O read command changes SI/SIO0 and SO/SIO1 into the input output pin function, makes the data input
and output x2 bit and has achieved a high-speed output. Consisting of the first through third bus cycles, the Dual I/O
read command inputs the 24-bit addresses and 4 dummy clocks following (BBh). The format of the address input
and the dummy bit input is the x2 bit input. Add1 (A23, A21, -, A3 and A1) is input from S0/SIO1 and Add0 (A22,
A20, -, A2 and A0) is input from SI/SIO0. 2CLK of the latter half of the dummy clock is in the state of high
impedance, the controller can switch I/O for this period. DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0
and DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of third bus cycle bit 0 as a
reference. "Figure 5-b Dual I/O Read" shows the timing waveforms.
Figure 5-b Dual I/O Read
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
CS
High Impedance
DATA1 DATA1
DATA1
SCK
SO/SIO1
SI/SIO0
3Bh
A
dd.
A
dd.
A
dd.
15
MSB MSB
0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 43 44 47
Mode3
Mode0
8CL
MSB
MSB
N+2
N+1
N
DATA0 DATA0 DATA0
4CL
4CL
DATA0
b6,b4,b2,b0
DATA1
b7,b5,b3,b1
dummy
bit
CS
High Impedance
DATA1 DATA1
DATA1
SCK
SO/SIO1
SI/SIO0
BBh
X
A
dd1:A22,A20-A2,A0
MSB MSB
0 1 2 3 4 5 6 7 8
19
22 23 24 27 28 31
Mode3
Mode0
8CL
MSB
MSB
N+2
N+1
N
DATA0 DATA0 DATA0
4CLK
DATA0
b6,b4,b2,b0
DATA1
b7,b5,b3,b1
dummy
bit
20 21
A
dd2:A23,A21-A3,A1
X
2CLK
2CLK
12CLK
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8
3. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
4 Status registers" gives the significance of each bit.
Table 4 Status Registers
Bit Name Logic Function Power-on Time Information
Bit0
RDY
0 Ready
0
1 Erase/Program
Bit1 WEN
0 Write disabled
0
1 Write enabled
Bit2 BP0
0
Block protect information
Protecting area switch
Nonvolatile information
1
Bit3 BP1
0
Nonvolatile information
1
Bit4 BP2
0
Nonvolatile information
1
Bit5 TB
0
Block protect
Upper side/Lower side switch
Nonvolatile information
1
Bit6 Reserved bits 0
Bit7 SRWP
0 Status register write enabled
Nonvolatile information
1 Status register write disabled
3-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY
(bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY
(bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 6 Status Register Read
CS
SCK
SI
SO
MSB MSB MSB
05h
DATA DATA
High Impedance
8 3 2 1 0 7 6 5 4 15
23
Mode 3
Mode 0
8CLK
16
DATA
MSB
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3-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY
, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2,
TB and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained
even at power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and
Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register
write command initiates the internal write operation at the rising CS
edge after the data has been input following
(01h). Erase and program are performed automatically inside the device by status register write so that erasing or
other processing is unnecessary before executing the command. By the operation of this command, the information
in bits BP0, BP1, BP2, TB and SRWP can be rewritten. Since bits RDY
(bit 0), WEN (bit 1) and bit 6 of the status
register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the
status register. Status register write ends can be detected by RDY
of status register read. To initiate status register
write, the logic level of the WP
pin must be set high and status register WEN must be set to "1".
Figure 6 Status Register Write
3-3. Contents of each status register
RDY
(Bit 0)
The RDY
register is for detecting the write (program, erase and status register write) end. When it is "1", the device
is in a busy state, and when it is "0", it means that write is completed.
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will
not perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following
states, WEN is automatically set to "0" in order to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a write operation has not been performed inside the LE25U40CQH because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior
to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
t
SRW
Self-timed
Write Cycle
SCK
SI
High Impedance
SO
CS
DATA 01h
150 1 2 3 4 5 6 7 8
Mode3
Mode0
8CLK
WP
t
WPH
t
WPS
MSB
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LE25U40CQH-AH

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Manufacturer:
ON Semiconductor
Description:
NOR Flash FLASH MEMORY
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