13
FN7493.3
April 24, 2009
Buck Converter
The buck converter is the step down converter, which
supplies the current to the logic circuit of the LCD system.
The ISL97651 integrates an 20V N-Channel MOSFET to
save cost and reduce external component count. In the
continuous current mode, the relationship between input
voltage and output voltage is shown in Equation 9:
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of buck
converter is lower than input voltage.
The peak current limit of buck converter is set to 2A, which
restricts the maximum output current (average) based on the
Equation 10:
Where I
PP
is the ripple current in the buck inductor as the
Equation 11:
Where L is the buck inductor, f
s
is the switching frequency
(1.2MHz).
Feedback Resistors
The buck converter output voltage is determined by the
Equation 12:
Where R14 and R15 are the feedback resistors of buck
converter to set the output voltage current drawn by the
resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 1k is recommended.
Buck Converter Input Capacitor
The capacitor should support the maximum AC RMS current
which happens when D = 0.5 and maximum output current.
Where I
O
is the output current of the buck converter. Table 6
shows some recommendations for input capacitor.
Buck Inductor
An inductor value in the range 3.3µH to 10µH is
recommended for the buck converter. Besides the
inductance, the DC resistance and the saturation current
should also be considered when choosing buck inductor.
Low DC resistance can help maintain high efficiency, and the
saturation current rating should be at least 2A. Table 7
shows some recommendations for buck inductor.
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and
low forward voltage. The reverse voltage rating should be
higher than the maximum input voltage. The peak current
rating is 2A, and the average current should be as the
Equation 14:
Where I
O
is the output current of buck converter. Table 8
shows some diode recommended.
FIGURE 12. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
INTERSIL
ISL97651
LX1, LX2
FBB
A
VDD
V
IN
V
LOGIC
V
IN
----------------------
D=
(EQ. 9)
I
OMAX
2A I
pp
=
(EQ. 10)
I
pp
V
LOGIC
Lf
s
----------------------
1D=
(EQ. 11)
V
LOGIC
R
14
R
15
+
R
15
---------------------------
V
REF
=
(EQ. 12)
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION
CAPACITOR SIZE VENDOR PART NUMBER
10µF/16V 1206 TDK C3216X7R1C106M
10µF/10V 0805 Murata GRM21BR61A106K
22µF/16V 1210 Murata C3225X7R1C226M
TABLE 7. BUCK INDUCTOR RECOMMENDATION
INDUCTOR
DIMENSIONS
(mm) VENDOR PART NUMBER
4.7µH/2.7A
PEAK
5.7x5.0x4.7 Murata LQH55DN4R7M01K
6.8µH/3A
PEAK
7.3x6.8x3.2 TDK RLF7030T-6R8M2R8
10µH/2.4A
PEAK
12.95x9.4x3.0 Coilcraft DO3308P-103
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
DIODE
V
R
/I
AVG
RATING PACKAGE VENDOR
PMEG2020EJ 20V/2A SOD323F Philips Semiconductors
SS22 20V/2A SMB Fairchild Semiconductor
I
ACRMS
C
IN
 D1D I
O
=
(EQ. 13)
I
AVG
1D*I
o
=
(EQ. 14)
ISL97651
14
FN7493.3
April 24, 2009
Output Capacitor (Buck Converter)
Four 10µF or two 22µF ceramic capacitors are
recommended for this part. The overshoot and undershoot
will be reduced with more capacitance, but the recovery time
will be longer.
PI Loop Compensation (Buck Converter)
The buck converter of ISL97651 can be compensated by a
RC network connected from CM2 pin to ground. C9 = 4.7nF
and R2 = 2k RC network is used in the demo board. The
larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
The stability can be optimized in a similar manner to that
described in “PI Loop Compensation (Boost Converter)” on
page 12.
Bootstrap Capacitor (C16)
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
1µF is recommended for ISL97651. A low value capacitor
can lead to overcharging and in turn damage the part.
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if V
IN
- V
BUCK
< 1.5V, the internal MOSFET pull-
up device may be unable to turn-on until V
LOGIC
falls.
Hence, there is a minimum load requirement in this case.
The minimum load can be adjusted by the feedback
resistors to FBL.
The bootstrap capacitor can only be charged when the
higher side MOSFET is off. If the load is too light which can
not make the on time of the low side diode be sufficient to
replenish the boot strap capacitor, the MOSFET can’t turn
on. Hence there is minimum load requirement to charge the
bootstrap capacitor properly.
Linear-Regulator Controllers (V
ON
and V
OFF
)
The ISL97651 include 2 independent charge pumps (see
Figure 13). The negative charge pump inverters the V
SUP
voltage and provides a regulated negative output voltage.
The positive charge pump doubles or triples the V
SUP
voltage and provides a regulated positive output voltage.
The regulation of both the negative and positive charge
pumps is generated by internal comparator that senses the
output voltage and compares it with the internal reference.
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps can
provide 30mA for V
OFF
and 20mA for V
ON
.
The positive charge pump can generate double or triple
V
SUP
voltage depending on the configuration of C2+ and
C2- pins. If the C2+ pin connects to C1+, it is the voltage
doubler, and if C2+ connects C2- via a capacitor, it
configured a voltage tripler.
Positive Charge Pump Design Consideration
The positive charge pump integrates all the diodes (D1, D2
and D3 shown in the block diagram in Figure 13) required for
x2 (V
SUP
doubler) and x3 (V
SUP
tripler) modes of operation.
During the chip start-up sequence the mode of operation is
automatically detected when the charge pump is enabled.
With both C7 and C8 present, the x3 mode of operation is
detected. With C7 present, C8 open and with C1+ shorted to
C2+, the x2 mode of operation will be detected.
Due to the internal switches to V
SUP
(M1, M2 and M3),
P
OUT
is independent of the voltage on V
SUP
until the charge
pump is enabled. This is important for TFT applications
where the negative charge pump output voltage (V
OFF
) and
A
VDD
supplies need to be established before P
OUT
.
The maximum P
OUT
charge pump current can be estimated
from Equation 15 assuming a 50% switching duty:
Note: V
DIODE
(2 • I
MAX
) is the on-chip diode voltage as a
function of I
MAX
and V
DIODE
(40mA) < 0.7V.
In voltage doubler configuration, the maximum V
ON
is as
given by Equation 16:
For Voltage Tripler:
V
ON
output voltage is determined by Equation 18:
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR SIZE VENDOR PART NUMBER
10µF/6.3V 0805 TDK C2012X5R0J106M
10µF/6.3V 0805 Murata GRM21BR60J106K
22µF/6.3V 1210 TDK C3216X5R0J226M
100µF/6.3V 1206 Murata GRM31CR60J107M
I
MAX
2xmin of 50mA or
2V
SUP
2 V
DIODE
2I
MAX
VV
ON

22R
ONH
R
ONL
+
----------------------------------------------------------------------------------------------------------------------
0.95A
I
MAX
3xmin of 50mA or
3V
SUP
3 V
DIODE
2I
MAX
VV
ON

23R
ONH
2R
ONL
+
----------------------------------------------------------------------------------------------------------------------
0.95V
(EQ. 15)
V
ON_MAX(2x)
2V
SUP
V
DIODE
 2I
OUT
2r
ONH
r
ONL
+=
(EQ. 16)
V
ON_MAX(3x)
3V
SUP
V
DIODE
 2I
OUT
3r
ONH
2r
ONL
+=
(EQ. 17)
V
ON
V
FBP
1
R
8
R
9
-------
+



=
(EQ. 18)
ISL97651
15
FN7493.3
April 24, 2009
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher
M1, M2 which drives external steering diodes D2 and D3 via
a pump capacitor (C12) to generate the negative V
OFF
supply. An internal comparator (A1) senses the feedback
voltage on FBN and turns on M1 for a period up to half a
CLK period to maintain V
(FBN)
in regulated operation at
0.2V. External feedback resistor R6 is referenced to V
REF
.
Faults on V
OFF
which cause V
FBN
to rise to more than 0.4V,
are detected by comparator (A2) and cause the fault
detection system to start a fault ramp on C
DLY
pin which will
cause the chip to power down if present for more than the
time TFD (see "Electrical Specification" on page 2 and also
Figure 15).
The maximum V
OFF
output voltage of a single stage charge
pump is:
R6 and R7 in the “Typical Application Diagram” on page 10
determine V
OFF
output voltage.
Improving Charge Pump Noise Immunity
Depending on PCB layout and environment, noise pick-up at
the FBP and FBN inputs, which may degrade load regulation
performance, can be reduced by the inclusion of capacitors
across the feedback resistors (e.g. in the “Typical Application
Diagram” on page 10, C21 and C22 for the positive charge
pump). Set R6 • C20 = R7 • C19 with C19 ~ 100pF.
FIGURE 13. V
ON
FUNCTION DIAGRAM
VSUP
VSUP
VSUP
C1-
POUT
FBP
Control
C1+
C2-
C2+
D3 D2 D1
M2
M4
M1
M3
M5
VREF
1.2MHz
x2 Mode
x3 Mode
Both
External Connections
and Components
0.9V
C7
C8
C14
C21
R8
R9
C22
Error
FB
V
OFF
V
FBN
1
R7
R6
--------
+


V
REF
R7
R6
--------


=
(EQ. 20)
ISL97651

ISL97651ARTZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Display Drivers & Controllers ISL97651ARTZ 4-CH IN TEGRTD LCD SUPY
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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