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ISL97651ARTZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
4
FN7493.3
April 24, 2009
POSITIVE (V
ON
) CHARGE PUMP
V
ON
V
ON
Output Voltage Range 2X or 3X Charge Pump V
SUP
+2V 34 V
I
LOAD_PCP_MIN
External Load Driving Capability V
ON
= 25V (2X Charge Pump) 20 mA
V
ON
= 34V (3X Charge Pump) 20 mA
r
ON(VSUP_SW)
ON-Resistance of V
SUP
Input Switch I
(SWITCH)
= +40mA 10 17
r
ON(C1/2-)H
High-Side Driver ON-Resistance at
C1- and C2-
I
(C1/2-)
= +40mA 10 20
r
ON(C1/2-)L
Low-Side Driver ON-Resistance at
C1- and C2-
I
(C1/2-)
= -40mA 4 7
I
PU(VSUP_SW)
Pull-Up Current Limit in V
SUP
Input
Switch
V
(C2+)
= 0V to V
(SUP)
- 0.4V - V
(DIODE)
40 100 mA
I
PU(C1/2-)
Pull-Up Current Limit in C1- and C2- V
(C1/2-)
= 0V to V
(VSUP)
- 0.4V 40 100 mA
I
PD(C1/2-)
Pull-Down Current Limit in C1- and
C2-
V
(C1/2-)
= 0.2V to V
(VSUP)
-100 -40 mA
I
(POUT)LEAK
Leakage Current in P
OUT
EN = LOW -5 5 µA
V
FBP
FBP Regulation Voltage I
DRVP
= 0.2mA, T
A
= +25°C 1.176 1.2 1.224 V
I
DRVP
= 0.2mA 1.172 1.2 1.228 V
ACCP V
ON
Output Accuracy I
ON
= 1mA, T
A
= +25°C -2 +2 %
D_PCP_max Max Duty Cycle of the Positive
Charge Pump
50 %
V
(DIODE)
Internal Schottky Diode Forward
Voltage
I
(DIODE)
= +40mA 600 850 mV
ENABLE INPUTS
VHI-EN Enable “HIGH” 2.2 V
VLO_EN Enable “LOW” 0.8 V
IEN_pd Enable Pin Pull-Down Current V
EN
> VLO_EN 25 µA
VHI-ENL Logic Enable “HIGH” 2.2 V
VLO-ENL Logic Enable “LOW” 0.8 V
IENL_pd Logic Enable Pin Pull-Down Current V
ENL
> VLO_ENL 25 µA
V
ON
SLICE Positive Supply = V
(POUT)
I
(POUT)_SLICE
V
ON
slice Current from P
OUT
Supply CTL = VDD, sequence complete 100 200 µA
CTL = AGND, sequence complete 90 120 µA
r
ON(POUT-COM)
ON-Resistance between P
OUT
-
COM
CTL = VDD, sequence complete 5 10
r
ON(DRN-COM)
ON-Resistance between DRN -
COM
CTL = ACGND, sequence complete 30 60
r
ON_COM
ON-Resistance between COM and
PGND3
During start-up sequence 200 500 1500
VLO CTL Input LOW Voltage V
IN
= 4V to 5.5V 0.8 V
VHI CTL Input HIGH Voltage V
IN
= 4V to 5.5V 2.2 V
Electrical Specifications V
IN
= 5V, V
BOOST
= V
SUP
= 15V, V
ON
= 25V, V
OFF
= -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
ISL97651
5
FN7493.3
April 24, 2009
FAULT DETECTION THRESHOLDS
T_off Thermal Shut-Down (latched and
reset by power cycle or EN cycle)
Temperature rising 150 °C
Vth_A
VDD
(FBB) A
VDD
Boost Short Detection V
(FBB)
falling less than 0.9 V
Vth_V
LOGIC
(FBL) V
LOGIC
Buck Short Detection V
(FBL)
falling less than 0.9 V
Vth_P
OUT
(FBP) P
OUT
Charge Pump Short Detection V
(FBP)
falling less than 0.9 V
Vth_N
OUT
(FBN) N
OUT
Charge Pump Short Detection V
(FBN)
rising more than 0.4 V
t
FD
Fault Delay Time to Chip Turns Off C
DEL
= 220nF 52 ms
START-UP SEQUENCING
t
START-UP
Enable to A
VDD
Start Time C
DEL
= 220nF 80 ms
I
DELB_ON
DELB Pull-Down Current or
Resistance when Enabled by the
Start-Up Sequence
VDELB > 0.9V 36 50 70 µA
VDELB < 0.9V 1000 1326 1750
I
DELB_OFF
DELB Pull-Down Current or
Resistance when Disabled
VDELB < 20V 500 nA
t
VOFF
A
VDD
to V
OFF
C
DEL
= 220nF 9 ms
t
VON
V
OFF
to V
ON
Delay C
DEL
= 220nF 20 ms
t
VON-SLICE
V
ON
to V
ON-SLICE
Delay C
DEL
= 220nF 17 ms
Electrical Specifications V
IN
= 5V, V
BOOST
= V
SUP
= 15V, V
ON
= 25V, V
OFF
= -8V, over-temperature from -40°C to +105°C; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
FIGURE 1. A
VDD
EFFICIENCY vs I
OUT
FIGURE 2. A
VDD
LOAD REGULATION vs I
OUT
EFFICIENCY (%)
0
20
40
60
80
100
0 200 400 600 800 1000
I
OUT
(mA)
V
IN
= 5V, A
VDD
= 15V
-0.20
-0.10
0
0.10
-0.35
-0.15
-0.05
0.05
0 200 400 600 800 1000 1200
I
OUT
(mA)
A
VDD
LOAD REGULATION (%)
V
IN
= 5V, A
VDD
= 15V
-0.25
-0.30
ISL97651
6
FN7493.3
April 24, 2009
FIGURE 3. A
VDD
TRANSIENT RESPONSE FIGURE 4. V
LOGIC
EFFICIENCY vs OUTPUT CURRENT
FIGURE 5. V
LOGIC
LOAD REGULATION vs OUTPUT CURRENT FIGURE 6. V
LOGIC
TRANSIENT RESPONSE
FIGURE 7. V
ON
LOAD REGULATION vs I
ON
FIGURE 8. V
LOGIC
LOAD REGULATION vs OUTPUT
CURRENT
Typical Performance Curves (Continued)
1ms/DIV
CH1 = A
VDD
(200mV/DIV), CH2 = I
AVDD
(200mA/DIV)
L1 = 10µH, C
OUT
= 40µF, CM1 = 4.7nF, RM1
0
20
40
60
80
100
OUTPUT CURRENT (mA)
V
LOGIC
EFFICIENCY (%)
90
70
50
30
10
0 500 1000 1500 2000
V
IN
= 5V, V
LOGIC
= 3.3V
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0 500 1000 1500 2000 2500
OUTPUT CURRENT (mA)
V
LOGIC
LOAD REGULATION (%)
V
IN
= 5V, V
LOGIC
= 3.3V
1ms/DIV
CH1 = V
LOGIC
(50mV/DIV), CH2 = I
LOGIC
(200mA/DIV)
L2 = 6.8µH, C
OUT
= 30µF, CM2 = 4.7nF, RM2
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
0
0 102030405060
I
ON
(mA)
V
ON
LOAD REGULATION (%)
V
ON
= 25V
-0.05
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
OUTPUT CURRENT(mA)
V
LOGIC
LOAD REGULATION (%)
V
IN
= 5V, V
LOGIC
= 3.3V
ISL97651
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ISL97651ARTZ-T

Mfr. #:
Buy ISL97651ARTZ-T
Manufacturer:
Renesas / Intersil
Description:
Display Drivers & Controllers ISL97651ARTZ 4-CH IN TEGRTD LCD SUPY
Lifecycle:
New from this manufacturer.
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