MAX5170/MAX5172
Low-Power, Serial, 14-Bit DACs
with Voltage Output
14 ______________________________________________________________________________________
Offset and Buffer Configurations
The simple circuit of Figure 7 illustrates how to intro-
duce an offset to the output voltage. The amount of off-
set introduced by a voltage at the OS pin is shown in
the following equation:
V
OFFSET
= V
OS
x (1 - Gain)
where Gain = 1.638. However, the total output voltage
of the device cannot exceed V
DD
regardless of the volt-
age on the OS pin.
To set the gain of the output amplifier to 1, connect OS
to OUT.
Daisy-Chaining Devices
The serial data output pin (DOUT) allows multiple
MAX5170/MAX5172s to be daisy-chained together, as
shown in Figure 9. The advantage of this is that only two
lines are needed to control all the DACs on the line. The
disadvantage is that it takes n commands to program the
DACs. Figure 10 shows several MAX5170/MAX5172s
sharing one common DIN signal line. In this configura-
tion, the data bus is common to all devices. However,
more I/O lines are required for this configuration because
each device requires a dedicated CS line. The advan-
tage of this configuration is that only one command is
needed to program any DAC.
Using an AC Reference
The MAX5170/MAX5172 accepts reference voltages with
AC components as long as the reference voltage
remains between 0 and V
DD
- 1.4V. Figure 11 shows a
technique for applying an offset sine wave signal to REF.
The reference voltage must remain above AGND.
Power-Supply and Layout Considerations
Wire-wrap boards are not recommended. For optimum
system performance, use printed circuit boards with
separate analog and digital ground planes. Connect the
two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
pins together and connecting that point to the system
analog ground plane. This is useful because if the DAC’s
DGND is connected to the system digital ground, digital
noise may get through to the DAC’s analog portion.
Bypass the power supply with a 4.7µF capacitor in paral-
lel with a 0.1µF capacitor to AGND. Minimize their lead
lengths to reduce inductance. If noise becomes an
issue, use shielding and/or ferrite beads to increase iso-
lation.
To maintain INL and DNL performance as well as gain
drift, it is extremely important to provide the lowest possi-
ble reference output impedance at the DAC reference
input pin. INL degrades if the series resistance on REF
pin exceeds 0.1Ω. The same consideration must be
made for the AGND pin.
