LTC3900IS8#TRPBF Datasheet LTC3900ES8#PBF, LTC3900HS8#PBF, LTC3900MPS8#PBF | P7-P9

LTC3900

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applicaTions inForMaTion

Overview

In a typical forward converter topology, a power trans-

former is used to provide the functions of input/output

isolation and voltage step-down to achieve the required

low output voltage. Schottky diodes are often used on

the secondary-side to provide rectiﬁcation. Schottky

diodes, though easy to use, result in a loss of efﬁciency

due to relatively high voltage drops. To improve efﬁciency,

synchronous output rectiﬁers utilizing N-channel MOSFETs

can be used instead of Schottky diodes. The LTC3900

provides all of the necessary functions required to drive

the synchronous rectiﬁer MOSFETs.

Figure 1 shows a simpliﬁed forward converter application.

T1 is the power transformer; Q1 is the primary-side power

transistor driven by the primary controller, LT1952 output

(OUT). The pulse transformer T2 provides synchronization

and is driven by LT1952 synchronization signal, S

OUT

or SG

from the primary controller. Q3 and Q4 are secondary-side

synchronous switches driven by the LTC3900’s FG and CG

output. Inductor L

and capacitor C

OUT

form the output

ﬁlter to provide a steady DC output voltage for the load.

Also shown in Figure 1 is the feedback path from V

OUT

through the optocoupler driver LT4430 and an optocoupler,

back to the primary controller to regulate V

OUT

Each full cycle of the forward converter operation con-

sists of two periods. In the ﬁrst period, Q1 turns on and

the primary-side delivers power to the load through T1.

SG goes high and T2 generates a negative pulse at the

LTC3900 SYNC input. The LTC3900 forces FG to turn on

and CG to turn off, Q3 conducts. Current ﬂows to the

load through Q3, T1 and L

. In the next period, Q1 turns

off, SG goes low and T2 generates a positive pulse at the

LTC3900 SYNC input. The LTC3900 forces FG to turn off

and CG to turn on, Q4 conducts. Current continues to

ﬂow to the load through Q4 and L

. Figure 2 shows the

LTC3900 synchronization waveforms.

External MOSFET Protection

A programmable timer and a differential input current sense

comparator are included in the LTC3900 for protection

of the external MOSFET during power down and Burst

Mode

operation. The chip also shuts off the MOSFETs

if V

< 4.1V.

When the primary controller is powering down, the primary

controller shuts down ﬁrst and the LTC3900 continues to

operate for a while by drawing power from the V

bypass

cap, C

VCC

. The SG signal stops switching and there is no

SYNC pulse to the LTC3900. The LTC3900 keeps one of

the drivers turned on depending on the polarity of the

last SYNC pulse. If the last SYNC pulse is positive, CG

will remain high and the catch MOSFET, Q4 will stay on.

The inductor current will start falling down to zero and

continue going in the negative direction due to the voltage

that is still present across the output capacitor (the current

now ﬂows from C

OUT

back to L

). If Q4 is turned off while

the inductor current is negative, the inductor current will

produce high voltage across Q4, resulting in a MOSFET

avalanche. Depending on the amount of energy stored in

the inductor, this avalanche energy may damage Q4.

Figure 2. Synchronization Waveforms

GATE

(OUT)

OUT

)

SYNC

3900 F02

LTC3900

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applicaTions inForMaTion

The timer circuit and current sense comparator in LTC3900

are used to prevent reverse current buildup in the output

inductor.

Timer

Figure 3 shows the LTC3900 timer internal and external

circuits. The timer operates by using an external R-C

charging network to program the time-out period. On

every negative transition at the SYNC input, the chip

generates a 200ns pulse to reset the timer cap. If the

SYNC signal is missing or incorrect, allowing the timer

cap voltage to go high, it shuts off both drivers once the

voltage reaches the time-out threshold. Figure 4 shows

the timer waveforms.

A typical forward converter cycle always turns on Q3

and Q4 alternately and the SYNC input should alternate

between positive and negative pulses. The LTC3900 timer

also includes sequential logic to monitor the SYNC input

sequence. If after one negative pulse, the SYNC compara-

tor receives another negative pulse, the LTC3900 will not

reset the timer cap. If no positive SYNC pulse appears,

both drivers are shut off once the timer times out. Once

positive pulses reappear the timer resets and the drivers

start switching again. This is to protect the external com-

ponents in situations where only negative SYNC pulse is

present and FG output remains high. Figure 5 shows the

timer waveforms with incorrect SYNC pulses.

The LTC3900 has two separate SYNC comparators (S

and

–

in the Block Diagram) to detect the positive and negative

pulses. The threshold voltages of both comparators are

Figure 3. Timer Circuit

TMR

3900 F03

TMR

R1R2

TIMEOUT

TIMER

RESET

designed to be of the same magnitude (1.4V typical) but

opposite in polarity. In some situations, for example dur-

ing power up or power down, the SYNC pulse magnitude

may be low, slightly higher or lower than the threshold of

the comparators. This can cause only one of the SYNC

comparators to trip. This also appears as incorrect SYNC

pulse and the timer will not reset.

The timeout period is determined by the external R

TMR

and C

TMR

values and is independent of the V

voltage.

This is achieved by making the timeout threshold a ratio

of V

. The ratio is 0.2x, set internally by R1 and R2 (see

Figure 3). The timeout period should be programmed to

be around one period of the primary switching frequency

using the following formula:

TIMEOUT = 0.2 • R

TMR

• C

TMR

+ 0.27E-6

To reduce error in the timeout setting due to the discharge

time, select C

TMR

between 100pF and 1000pF. Start with a

TMR

around 470pF and then calculate the required R

TMR

should be placed as close as possible to the LTC3900

with minimum PCB trace between C

TMR

, the TIMER pin

and GND. This is to reduce any ringing caused by the PCB

trace inductance when C

TMR

discharges. This ringing may

introduce error to the timeout setting.

The timer input also includes a current sinking clamp

circuit (Z

TMR

in Figure 3) that clamps this pin to about

0.5 • V

if there is missing SYNC/timer reset pulse. This

clamp circuit prevents the timer cap from getting fully

charged up to the rail, which results in a longer discharge

SYNC

TIMER RESET

(INTERNAL)

TIMER

TIMEOUT

THRESHOLD

LAST

PULSE

3900 F04

Figure 4. Timer Waveforms

LTC3900

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applicaTions inForMaTion

time. The current sinking capability of the circuit is around

1mA. The timeout function can be disabled by connecting

the timer pin to GND.

Current Sense

The differential input current sense comparator is used

for sensing the voltage across the drain-to-source termi-

nals of Q4 through the CS

and CS

–

pins. If the inductor

current reverses into the Q4 causing CS

to rise above

–

by more than 10.5mV, the LTC3900 pulls CG low. This

comparator is used to prevent inductor reverse current

buildup during power down or Burst Mode operation, which

may cause damage to the MOSFET. The 10.5mV input

threshold has a positive temperature coefﬁcient, which

closely matches the TC of the external MOSFET R

DS(ON)

The current sense comparator is only active 250ns after

CG goes high; this is to avoid any ringing immediately

after Q4 is switched on.

Under light load conditions, if the inductor average cur-

rent is less than half of its peak-to-peak ripple current,

the inductor current will reverse into Q4 during a portion

of the switching cycle, forcing CS

to rise above CS

–

The current sense comparator input threshold is set at

10.5mV to prevent tripping under light load conditions.

If the product of the inductor negative peak current and

MOSFET R

DS(ON)

is higher than 10.5mV, the LTC3900 will

operate in discontinuous current mode. Figure 6 shows

the LTC3900 operating in discontinuous current mode;

the CG output goes low before the next negative SYNC

pulse, as soon as the inductor current becomes negative.

Discontinuous current mode is sometimes undesirable.

To disable discontinuous current mode operation, add a

resistor divider, R

CS1

and R

CS2

at the CS

pin to increase

the 10.5mV threshold so that the LTC3900 operates in

continuous mode at no load.

The LTC3900 CS

pin has an internal current sinking

clamp circuit (Z

in the Block Diagram) that clamps the

pin to 11V. The clamp circuit is to be used together with

the external series resistor, R

CS1

to protect the CS

from high Q4 drain voltage in the power transfer cycle.

During the power transfer cycle, Q4 is off, the drain volt-

age of Q4 is determined by the primary input voltage and

the transformer turns ratio. This voltage can be high and

may damage the LTC3900 if CS

is connected directly to

the drain of Q4. The current sinking capability of the clamp

circuit is 5mA minimum.

SYNC

TIMER RESET

(INTERNAL)

TIMER

TIMEOUT

THRESHOLD

3900 F05

TIMEOUT

MISSING/LOW

POSITIVE

SYNC PULSE

TIMER RESET AFTER

RECEIVING POSITIVE

SYNC PULSE

TIMER DO NOT RESET

AT SECOND NEGATIVE

SYNC PULSE

Figure 5. Timer Waveforms with Incorrect SYNC Pulses

SYNC

3900 F06a

INDUCTOR

CURRENT

CURRENT SENSE

COMPARATOR TRIP

Figure 6a. Discontinuous Current Mode Operation at No Load

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LTC3900IS8#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Gate Drivers Sync Rectifier Drvr for For Convs

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LTC3900IS8#TRPBF

LTC3900IS8#TRPBF

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