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CY7C1339G-133AXIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
4-Mbit (128K x 32) Pipelined Sync SRAM
CY7C1339G
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05520 Rev. *F Revised July 5, 2006
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC
, ADSP,
and
ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (
GW
). Asynchronous
inputs include the Output Enable (OE
) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
) or
Address Strobe Controller (ADSC
) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV
).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW
when active
LOW
causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
ADDR ESS
REGISTER
ADV
CLK
BURST
COUN T E R
AND
LOG IC
CLR
Q1
Q0
ADSP
ADSC
MODE
BW E
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SEN SE
AMPS
OUTPUT
BU FFERS
E
PIPELI N ED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRA Y
DQs
SLEEP
CON T RO L
ZZ
A
[1:0]
2
DQ
A
BYTE
W R ITE REG ISTE R
DQ
B
BYTE
WRITE REGISTER
DQ
C
BYTE
W R ITE REG ISTE R
DQ
D
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE DRIVER
DQ
B
BYTE
WRITE DRIVER
DQ
C
BYTE
WRITE DRIVER
DQ
D
BYTE
WRITE DRIVER
Logic Block Diagram
[+] Feedback
CY7C1339G
Document #: 38-05520 Rev. *F Page 2 of 18
Pin Configurations
Selection Guide
250 MHz 200 MHz 166 MHz 133 MHz Unit
Maximum Access Time 2.6 2.8 3.5 4.0 ns
Maximum Operating Current 325 265 240 225 mA
Maximum CMOS Standby Current 40 40 40 40 mA
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
A
A
A
A
A
A
A
NC
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
NC
NC
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
NC
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE A
BYTE B
BYTE D
BYTE C
CY7C1339G
100-Pin TQFP Pinout
[+] Feedback
CY7C1339G
Document #: 38-05520 Rev. *F Page 3 of 18
Pin Configurations (continued)
Pin Definitions
Name I/O Description
A
0
, A
1
, A Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP
or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A1, A0
are fed to the two-bit counter.
.
BW
A
, BW
B
BW
C
, BW
D
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV
is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
CE
1
is sampled only
when a new external address is loaded.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.CE
2
is sampled only when a new external address is
loaded.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is
loaded. Not connected for BGA. Where referenced, CE
3
is assumed active throughout this
document for BGA.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE
is masked during the first clock of a read cycle when emerging from a
deselected state.
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
NCDQ
C
DQ
D
DQ
C
DQ
D
AA AA
ADSP
V
DDQ
CE
2
A
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
NCNCNCNC
NC/36MNC/72M
NC
V
DDQ
V
DDQ
V
DDQ
AAA
A
NC/9M
AA
A
AA
A
A0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
NC
NC
BW
B
BW
c
NC V
DD
NC
BW
A
NC
BWE
BW
D
ZZ
119-Ball BGA Pinout
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CY7C1339G-133AXIT

Mfr. #:
Buy CY7C1339G-133AXIT
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 4M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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