Automotive PSoC
®
4: PSoC 4200
Family Datasheet
Programmable System-on-Chip (PSoC
®
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-93573 Rev. *E Revised March 28, 2017
Programmable System-on-Chip (PSoC
®
)
General Description
PSoC
®
4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM
®
Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and re-configurable analog
and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a
microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamp with Comparator mode, and
standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4
platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning
of the design.
Features
32-bit MCU Subsystem
■ Automotive Electronics Council (AEC) AEC-Q100 qualified
■ 48 MHz ARM Cortex-M0 CPU with single cycle multiply
■ Up to 32 kB of flash with Read Accelerator
■ Up to 4 kB of SRAM
Programmable Analog
■ One opamp with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator mode, and ADC
input buffering capability
■ 12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Two low-power comparators that operate in Deep Sleep
Programmable Digital
■ Four programmable logic blocks called universal digital blocks,
(UDBs), each with 8 Macrocells and data path
■ Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Low Power 1.71 to 5.5 V operation
■ 20-nA Stop Mode with GPIO pin wakeup
■ Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■ LCD drive supported on all pins (common or segment)
■ Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
■ Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, UART, or
LIN Slave 1.3, 2.1/2.2 functionality
Timing and Pulse-Width Modulation
■ Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM)
blocks
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 24 Programmable GPIOs
■ 28-pin SSOP package
■ Any GPIO pin can be CapSense, LCD, analog, or digital
■ Drive modes, strengths, and slew rates are programmable
Temperature Ranges:
■ A Grade: –40 °C to +85 °C
■ S Grade: –40 °C to +105 °C
PSoC Creator Design Environment
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
■ After schematic entry, development can be done with
ARM-based industry-standard development tools
