Automotive PSoC
®
4: PSoC 4200
Family Datasheet
Document Number: 001-93573 Rev. *E Page 4 of 37
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in PSoC 4200 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG; the debug
configuration used for PSoC 4200 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The PSoC 4200 device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS
access time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
The PSoC 4200 flash supports the following flash protection
modes at the Memory subsystem level.
Open: No Protection. Factory default mode that the product is
shipped in.
Protected: User may change from Open to Protected. This
mode disables Debug interface accesses. The mode can be set
back to Open but only after completely erasing the flash.
Kill: User may change from Open to Kill. This mode disables all
Debug accesses. The part cannot be erased externally thus
obviating the possibility of partial erasure by power interruption
and potential malfunction and security leaks. This is an
irrecvocable mode.
In addition, Row level Read/Write protection is also supported to
prevent inadvertent Writes as well as selectively block Reads.
Flash Read/Write/Erase operations are always available for
internal code using system calls.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section Power on
page 11. It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)).
PSoC 4200 operates with a single external supply over the range
of 1.71 V to 5.5 V and has five different power modes, transitions
between which are managed by the power system. The
PSoC 4200 provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Clock System
The PSoC 4200 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for PSoC 4200 consists of the IMO and the ILO
internal oscillators and provision for an external clock.
Figure 1. PSoC 4200 MCU Clocking Architecture
The HFCLK signal can be divided down (see PSoC 4200 MCU
Clocking Architecture) to generate synchronous clocks for the
UDBs, and the analog and digital peripherals. There are a total
of 12 clock dividers for PSoC 4200, each with 16-bit divide
capability; this allows eight to be used for the fixed-function
blocks and four for the UDBs. The analog clock leads the digital
clocks to allow analog events to occur before digital clock-related
noise is generated. The 16-bit capability allows a lot of flexibility
in generating fine-grained frequency values and is fully
supported in PSoC Creator. When UDB-generated Pulse
Interrupts are used, SYSCLK must equal HFCLK.
UDB
Dividers
Analog
Divider
Peripheral
Dividers
SYSCLK
PrescalerHFCLK
UDBn
SAR clock
PERXYZ_CLK
IMO
ILO
HFCLK
LFCLK
EXTCLK