CY8C4245PVA-482Z Datasheet CY8C4245PVA-482Z, CY8C4245PVA-482T, CY8C4245PVA-482ZT | P4-P6

Automotive PSoC

4: PSoC 4200

Family Datasheet

Document Number: 001-93573 Rev. *E Page 4 of 37

Functional Overview

CPU and Memory Subsystem

CPU

The Cortex-M0 CPU in PSoC 4200 is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and

executes a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a Wakeup

Interrupt Controller (WIC). The WIC can wake the processor up

from the Deep Sleep mode, allowing power to be switched off to

the main processor when the chip is in the Deep Sleep mode.

The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)

input, which is made available to the user when it is not in use

for system functions requested by the user.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a two-wire form of JTAG; the debug

configuration used for PSoC 4200 has four break-point (address)

comparators and two watchpoint (data) comparators.

Flash

The PSoC 4200 device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The flash block is designed to

deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS

access time at 24 MHz. The flash accelerator delivers 85% of

single-cycle SRAM access performance on average. Part of the

flash module can be used to emulate EEPROM operation if

required.

The PSoC 4200 flash supports the following flash protection

modes at the Memory subsystem level.

Open: No Protection. Factory default mode that the product is

shipped in.

Protected: User may change from Open to Protected. This

mode disables Debug interface accesses. The mode can be set

back to Open but only after completely erasing the flash.

Kill: User may change from Open to Kill. This mode disables all

Debug accesses. The part cannot be erased externally thus

obviating the possibility of partial erasure by power interruption

and potential malfunction and security leaks. This is an

irrecvocable mode.

In addition, Row level Read/Write protection is also supported to

prevent inadvertent Writes as well as selectively block Reads.

Flash Read/Write/Erase operations are always available for

internal code using system calls.

SRAM

SRAM memory is retained during Hibernate.

SROM

A supervisory ROM that contains boot and configuration routines

is provided.

System Resources

Power System

The power system is described in detail in the section Power on

page 11. It provides assurance that voltage levels are as required

for each respective mode and either delay mode entry (on

power-on reset (POR), for example) until voltage levels are as

required for proper function or generate resets (Brown-Out

Detect (BOD)) or interrupts (Low Voltage Detect (LVD)).

PSoC 4200 operates with a single external supply over the range

of 1.71 V to 5.5 V and has five different power modes, transitions

between which are managed by the power system. The

PSoC 4200 provides Sleep, Deep Sleep, Hibernate, and Stop

low-power modes.

Clock System

The PSoC 4200 clock system is responsible for providing clocks

to all subsystems that require clocks and for switching between

different clock sources without glitching. In addition, the clock

system ensures that no metastable conditions occur.

The clock system for PSoC 4200 consists of the IMO and the ILO

internal oscillators and provision for an external clock.

Figure 1. PSoC 4200 MCU Clocking Architecture

The HFCLK signal can be divided down (see PSoC 4200 MCU

Clocking Architecture) to generate synchronous clocks for the

UDBs, and the analog and digital peripherals. There are a total

of 12 clock dividers for PSoC 4200, each with 16-bit divide

capability; this allows eight to be used for the fixed-function

blocks and four for the UDBs. The analog clock leads the digital

clocks to allow analog events to occur before digital clock-related

noise is generated. The 16-bit capability allows a lot of flexibility

in generating fine-grained frequency values and is fully

supported in PSoC Creator. When UDB-generated Pulse

Interrupts are used, SYSCLK must equal HFCLK.

UDB

Dividers

Analog

Divider

Peripheral

Dividers

SYSCLK

PrescalerHFCLK

UDBn

SAR clock

PERXYZ_CLK

IMO

ILO

HFCLK

LFCLK

EXTCLK

Automotive PSoC

4: PSoC 4200

Family Datasheet

Document Number: 001-93573 Rev. *E Page 5 of 37

IMO Clock Source

The IMO is the primary source of internal clocking in PSoC 4200.

It is trimmed during testing to achieve the specified accuracy.

Trim values are stored in nonvolatile latches (NVL). Additional

trim settings from flash can be used to compensate for changes.

The IMO default frequency is 24 MHz and it can be adjusted

between 3 to 48 MHz in steps of 1 MHz. IMO Tolerance with

Cypress-provided calibration settings is ±2%.

ILO Clock Source

The ILO is a very low power oscillator, which is primarily used to

generate clocks for peripheral operation in Deep Sleep mode.

ILO-driven counters can be calibrated to the IMO to improve

accuracy. Cypress provides a software component, which does

the calibration.

Watchdog Timer

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the timeout

occurs. The watchdog reset is recorded in the Reset Cause

Reset

PSoC 4200 can be reset from a variety of sources including a

software reset. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause is recorded in a

determine the cause of the Reset. An XRES pin is reserved for

external reset to avoid complications with configuration and

multiple pin functions during power-on or reconfiguration. The

XRES pin has an internal pull-up resistor that is always enabled.

Voltage Reference

The PSoC 4200 reference system generates all internally

required references. A 1% voltage reference spec is provided for

the 12-bit ADC. To allow better signal to noise ratios (SNR) and

better absolute accuracy, it is possible to bypass the internal

reference using a GPIO pin or to use an external reference for

the SAR.

Analog Blocks

12-bit SAR ADC

The 12-bit 1 MSample/second SAR ADC can operate at a

maximum clock rate of 18 MHz and requires a minimum of 18

clocks at that frequency to do a 12-bit conversion.

The block functionality is augmented for the user by adding a

reference buffer to it (trimmable to ±1%) and by providing the

choice (for the PSoC 4200 case) of three internal voltage

references: V

, V

/2, and V

REF

(nominally 1.024 V) as well as

an external reference through a GPIO pin. The Sample-and-Hold

(S/H) aperture is programmable allowing the gain bandwidth

requirements of the amplifier driving the SAR inputs, which

determine its settling time, to be relaxed if required. System

performance will be 65 dB for true 12-bit precision providing

appropriate references are used and system noise levels permit.

To improve performance in noisy conditions, it is possible to

provide an external bypass (through a fixed pin location) for the

internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input

sequencer. The sequencer cycles through selected channels

autonomously (sequencer scan) and does so with zero switching

overhead (that is, aggregate sampling bandwidth is equal to

1 Msps whether it is for a single channel or distributed over

several channels). The sequencer switching is effected through

a state machine or through firmware driven switching. A feature

provided by the sequencer is buffering of each channel to reduce

CPU interrupt service requirements. To accommodate signals

with varying source impedance and frequency, it is possible to

have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers

(low and high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

The SAR is able to digitize the output of the on-board

temperature sensor for calibration and other

temperature-dependent functions. The SAR is not available in

Deep Sleep and Hibernate modes as it requires a high-speed

clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V.

Figure 2. SAR ADC System Diagram

SARMUX

Port 2 (8 inputs)

vplusvminus

Data and

Status Flags

Reference

Selection

External

Reference

and

Bypass

(optional)

POS

NEG

SAR Sequencer

SARADC

Inputs from other Ports

VDD/2

VDDD VREF

AHB System Bus and Programmable Logic

Interconnect

Sequencing

and Control

Automotive PSoC

4: PSoC 4200

Family Datasheet

Document Number: 001-93573 Rev. *E Page 6 of 37

Opamp (CTBm Block)

PSoC 4200 has an opamp with Comparator mode which allow

most common analog functions to be performed on-chip elimi-

nating external components; PGAs, Voltage Buffers, Filters,

Trans-Impedance Amplifiers, and other functions can be realized

with external passives saving power, cost, and space. The

on-chip opamp is designed with enough bandwidth to drive the

Sample-and-Hold circuit of the ADC without requiring external

buffering.

Temperature Sensor

PSoC 4200 has one on-chip temperature sensor This consists

of a diode, which is biased by a current source that can be

disabled to save power. The temperature sensor is connected to

the ADC, which digitizes the reading and produces a temper-

ature value using Cypress supplied software that includes

calibration and linearization.

Low-power Comparators

PSoC 4200 has a pair of low-power comparators, which can also

operate in the Deep Sleep and Hibernate modes. This allows the

analog system blocks to be disabled while retaining the ability to

monitor external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid metasta-

bility unless operating in an asynchronous power mode

(Hibernate) where the system wake-up circuit is activated by a

comparator switch event.

Programmable Digital

Universal Digital Blocks (UDBs) and Port Interfaces

PSoC 4200 has four UDBs; the UDB array also provides a

switched Digital System Interconnect (DSI) fabric that allows

signals from peripherals and ports to be routed to and through

the UDBs for communication and control. The UDB array is

shown in the following figure.

Figure 3. UDB Array

UDBs can be clocked from a clock divider block, from a port

interface (required for peripherals such as SPI), and from the DSI

network directly or after synchronization.

A port interface is defined, which acts as a register that can be

clocked with the same source as the PLDs inside the UDB array.

This allows faster operation because the inputs and outputs can

be registered at the port interface close to the I/O pins and at the

edge of the array. The port interface registers can be clocked by

one of the I/Os from the same port. This allows interfaces such

as SPI to operate at higher clock speeds by eliminating the delay

for the port input to be routed over DSI and used to register other

inputs (see Figure 4).

The UDBs can generate interrupts (one UDB at a time) to the

interrupt controller. The UDBs retain the ability to connect to any

pin on the chip through the DSI.

Figure 4. Port Interface

Programmable Digital Subsystem

UDBIF

UDB UDB

DSI DSI

BUS IF CLK IF

Port IF

High -S

peed I/O Matrix

CPU

Sub-system

System

Interconnect

Clocks

4 to 8

8 to 32

Routing

Channels

Other Digital

Signal s in Chip

IRQ IF

Clock Selector

Block from

UDB

Digital

GlobalClocks

3 DSI Signals ,

1 I/O Signal

Reset Selector

Block from

UDB

Input Registers Output Registers

To DSI

From DSI

8 8

Enables

From DSI

7 6 . . . 0 7 6 . . . 0 3 2 1 0

High Speed I/O Matrix

To Clock

Tree

[0]

[1]

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CY8C4245PVA-482Z

Mfr. #:

Buy CY8C4245PVA-482Z

Manufacturer:

Cypress Semiconductor

Description:

ARM Microcontrollers - MCU PSoC4

Lifecycle:

New from this manufacturer.

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CY8C4245PVA-482Z

CY8C4245PVA-482Z

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