8
FN6442.1
September 29, 2008
through a RC network to produce the desired sawtooth
waveform.
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR - These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input for closed loop regulation. VERR
has a nominal 1mA pull-up current source.
When VERR is driven by an opto-coupler or other current
source device, a pull-up resistor from VREF is required to
linearize the gain. Generally, a pull-up resistor on the order
of 5k is acceptable.
FB1,2 - FB1 and FB2 are the inverting inputs to the error
amplifiers (EA). The amplifier may be used as the error
amplifier for voltage feedback or used as the average current
limit amplifier (IEA). If the amplifier is not used, FB should be
grounded.
IOUT - Output of the 4X buffer amplifier of the sample and
hold circuitry that captures and averages the CS signal.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of
the capacitor and the internal current source determine the
rate of increase of the duty cycle during start-up.
SS may also be used to inhibit the outputs by grounding
through a small transistor in an open collector/drain
configuration.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The ISL6755 PWM is an excellent choice for low cost ZVS
full-bridge applications employing conventional output
rectification. If synchronous rectification is required, please
consider the ISL6752 or ISL6551 products.
With the ISL6755’s many protection and control features, a
highly flexible design with minimal external components is
possible. Among its many features are support for both
current- and voltage-mode control, a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
voltage controlled resonant delay, and adjustable frequency
with precise deadtime control.
Oscillator
The ISL6755 has an oscillator with a programmable
frequency range to 2MHz, and can be programmed with an
external resistor and capacitor.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200A internal current source.
The discharge duration is determined by RTD and CT.
where T
C
and T
D
are the charge and discharge times,
respectively, T
SW
is the oscillator period, and F
SW
is the
oscillator frequency. One output switching cycle requires two
oscillator cycles. The actual times will be slightly longer than
calculated due to internal propagation delays of
approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very small discharge currents are used, there
will be increased error due to the input impedance at the CT
pin.
T
C
11.5 10
3
CT S
(EQ. 1)
T
D
0.06 RTD CT50 10
9–
+ S
(EQ. 2)
T
SW
T
C
T
D
+
1
F
SW
------------
== S
(EQ. 3)
ISL6755
