LTC2436-1
7
24361f
Figure 1. Functional Block Diagram
1.69k
SDO
24361 TA03
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
24361 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
UU
W
FU CTIO AL BLOCK DIAGRA
AUTOCALIBRATION
AND CONTROL
DECIMATING FIR
CH0/CH1
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
PING-PONG
DIFFERENTIAL
3RD ORDER
Σ MODULATOR
+–
MUX
GND
REF
+
CH0
+
IN
+
IN
CH0
CH1
+
CH1
REF
V
CC
SCK
SDO
CS
F
O
(INT/EXT)
24361 FD
TEST CIRCUITS
LTC2436-1
8
24361f
CONVERTER OPERATION
Converter Operation Cycle
The LTC2436-1 is a low power, ∆Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2436-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
formed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2436-1 with
additional serial clock pulses. This results in additional
data bits which are always logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2436-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2436-1 incorporates a highly accu-
rate on-chip oscillator. This eliminates the need for exter-
nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2436-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.
Ease of Use
The LTC2436-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
Figure 2. LTC2436-1 State Transition Diagram
APPLICATIO S I FOR ATIO
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CONVERT
POWER UP
IN
+
= CH0
+
, IN
= CH0
SLEEP
DATA OUTPUT
SWITCH CHANNEL
24361 F02
TRUE
FALSE
CS = LOW
AND
SCK
LTC2436-1
9
24361f
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2436-1 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2436-1 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers and selects channel 0. Following the
POR signal, the LTC2436-1 starts a normal conversion
cycle and follows the succession of states described above.
The first conversion result following POR is accurate within
the specifications of the device if the power supply voltage
is restored within the operating range (2.7V to 5.5V) be-
fore the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF
+
and REF
pins covers the entire range
from GND to V
CC
. For correct converter operation, the
REF
+
pin must always be more positive than the REF
pin.
The LTC2436-1 can accept a differential reference voltage
from 0.1V to V
CC
. The converter output noise is deter-
mined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will
significantly improve the converter’s effective resolution,
since the thermal noise (800nV) is well below the quanti-
zation level of the device (75.6µV for a 5V reference). At the
minimum reference (100mV) the thermal noise
remains constant at 800nV RMS (or 4.8µV
P-P
), while the
quantization is reduced to 1.5µV per LSB. As a result,
lower the reference improves the effective resolution for
low level input voltages.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0
+
/CH0
or CH1
+
/CH1
input pins extending from GND – 0.3V to V
CC
+ 0.3V.
Outside these limits, the ESD protection devices begin to
turn on and the errors due to input leakage current
increase rapidly. Within these limits, the LTC2436-1 con-
verts the bipolar differential input signal, V
IN
= IN
+
– IN
,
from –FS = –0.5 • V
REF
to +FS = 0.5 • V
REF
where V
REF
=
REF
+
– REF
, with the selected channel referred as IN
+
and
IN
. Outside this range, the converter indicates the
overrange or the underrange condition using distinct
output codes.
Input signals applied to the analog input pins may extend
by 300mV below ground and above V
CC
. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to main-
tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
Current sections. In addition, series resistors will intro-
duce a temperature dependent offset error due to the input
leakage current. A 10nA input leakage current will develop
a 1LSB offset error on an 8k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2436-1 serial output data stream is 19 bits long.
The first 3 bits represent status information indicating the
conversion state, selected channel and sign. The next 16
bits are the conversion result, MSB first. The third and
fourth bit together are also used to indicate an underrange
condition (the differential input voltage is below –FS) or an
overrange condition (the differential input voltage is above
+FS).
APPLICATIO S I FOR ATIO
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LTC2436-1IGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2-Ch Diff In 16-B No Lat DS ADC
Lifecycle:
New from this manufacturer.
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