MJB5742T4G

MJB5742T4G
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4
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
RESISTIVE
SWITCHING
OUTPUT WAVEFORMS
TEST CIRCUITS
CIRCUIT
VALUES
TEST WAVEFORMS
NOTE:
PW and V
CC
Adjusted for Desired I
C
R
B
Adjusted for Desired I
B1
P
W
DUTY CYCLE 10%
t
r
, t
f
10 ns
68
1
k
0.001 mF
0.02 mF
1N493
3
270
+5 V
1
k
2N2905
47
1/2
W
100
-V
BE(off)
MJE20
0
T.U.T.
I
B
R
B
1N493
3
1N493
3
33
33
2N222
2
1
k
MJE21
0
V
CC
+5 V
L
I
C
MR826
*
V
clamp
*SELECTED FOR 1 kV
V
CE
5.1
k
51
+V
CC
R
C
SCOPE
-4 V
D
1
R
B
TUT
COIL DATA:
FERROXCUBE CORE #6656
FULL BOBBIN (~16 TURNS) #16
GAP FOR 200 mH/20 A
L
coil
= 200 mH
V
CC
= 30 V
V
CE(pk)
= 250 Vdc
I
C(pk)
= 6 A
V
CC
= 250 V
D1 = 1N5820 OR EQUIV.
I
C
V
CE
I
C(pk)
t
1
t
f
t
t
t
2
TIM
E
V
CE
OR
V
clamp
t
f
CLAMPED
t
1
ADJUSTED TO
OBTAIN I
C
t
1
L
coil
(I
C
pk
)
V
CC
t
2
L
coil
(I
C
pk
)
V
clamp
TEST EQUIPMENT
SCOPE-TEKTRONICS
475 OR EQUIVALENT
+10 V
25 ms
0
- 9.2 V
t
r
, t
f
< 10 ns
DUTY CYCLE = 1%
R
B
AND R
C
ADJUSTED
FOR DESIRED I
B
AND I
C
Table 1. Test Conditions for Dynamic Performance
MJB5742T4G
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5
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 6 is based on T
C
= 25_C; T
J(pk)
is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when T
C
25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 6 may be found at
any case temperature by using the appropriate curve on
Figure 1.
REVERSE BIAS
For inductive loads, high voltage and high current must be
sustained simultaneously during turnoff, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltagecurrent condition allowable
during reverse biased turnoff. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 7 gives the complete RBSOA
characteristics.
The Safe Operating Area figures shown in Figures 6 and 7 are specified ratings for these devices under the test conditions shown.
I
C
, COLLECTOR CURRENT (AMPS)
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 6. Forward Bias Safe Operating Area
Figure 7. Reverse Bias Safe Operating Area
16
14
12
8
0
2
4
10
100 200 300 5000 400
16
5
10
8
1
0.02
100
I
C
, COLLECTOR CURRENT (AMPS)
0.1
10 20 200 400
3
0.5
50
0.3
0.05
dc
1ms
100 ms
MJB5742
V
BE(off)
5 V
T
J
= 100°C
6
CURVES APPLY BELOW RATED V
CEO
10 ms
5ms
BONDING WIRE LIMIT
THERMAL LIMIT
(SINGLE PULSE)
SECOND BREAKDOWN LIMIT
t, TIME (s)μ
t, TIME (s)μ
I
C
, COLLECTOR CURRENT (AMPS)
0.5 0.7 1 2 10
7
5
2
1
0.7
0.2
0.3 5
0.5
10
3
3
0.3
0.2 7
I
C
, COLLECTOR CURRENT (AMPS)
0.5 0.7 1 2 10
0.7
0.5
0.2
0.1
0.07
0.02
0.3
Figure 8. TurnOn Time
5
0.05
1
Figure 9. TurnOff Time
3
V
CC
= 250 V
I
B1
= I
B2
I
C
/I
B
= 20
t
s
t
r
t
f
t
d
V
CC
= 250 V
I
B1
= I
B2
I
C
/I
B
= 20
0.3
0.03
0.2 7
RESISTIVE SWITCHING PERFORMANCE
MJB5742T4G
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6
PACKAGE DIMENSIONS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
SEATING
PLANE
S
G
D
T
M
0.13 (0.005) T
231
4
3 PL
K
J
H
V
E
C
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
D 0.020 0.035 0.51 0.89
E 0.045 0.055 1.14 1.40
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
J 0.018 0.025 0.46 0.64
K 0.090 0.110 2.29 2.79
S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40
B
M
B
W
W
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B01 THRU 418B03 OBSOLETE,
NEW STANDARD 418B04.
F 0.310 0.350 7.87 8.89
L 0.052 0.072 1.32 1.83
M 0.280 0.320 7.11 8.13
N 0.197 REF 5.00 REF
P 0.079 REF 2.00 REF
R 0.039 REF 0.99 REF
M
L
F
M
L
F
M
L
F
VARIABLE
CONFIGURATION
ZONE
R
N P
U
VIEW WW VIEW WW VIEW WW
123
D
2
PAK 3
CASE 418B04
ISSUE K
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8.38
5.080
DIMENSIONS: MILLIMETERS
PITCH
2X
16.155
1.016
2X
10.49
3.504

MJB5742T4G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Darlington Transistors BIP D2PAK XSTR TR
Lifecycle:
New from this manufacturer.
Delivery:
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