17
LTC2424/LTC2428
APPLICATIONS INFORMATION
WUU
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For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure 8,
for output data rates of 100 samples/second, the TUE is
better than 15 bits for V
REF
below 2.5V. Figure 9 shows an
unaveraged total unadjusted error for the LTC2424 or
LTC2428 operating at 100 samples/second with V
REF
=
2.5V. Figure 10 shows the same device operating with a 5V
reference and an output data rate of 7.5 samples/second.
At 100 samples/second, the LTC2424/LTC2428 can be
used to capture transient data. This is useful for monitor-
ing settling or auto gain ranging in a system. The LTC2424/
LTC2428 can monitor signals at an output rate of 100
samples/second. After acquiring 100 samples/second data,
the F
O
pin may be driven LOW enabling 60Hz rejection to
110dB and the highest possible DC accuracy. The no
latency architecture of the LTC2424/LTC2428 allows con-
secutive readings (one at 100 samples/second the next at
7.5 samples/second) without interaction between the two
readings.
As shown in Figure 11, the LTC2424/LTC2428 can cap-
ture transient data with 90dB of dynamic range (with a
300mV
P-P
input signal at 2Hz). The exceptional DC
performance of
the LTC2424/LTC2428 enables signals to
be digitized independent of a large DC offset. Figures 12a
and 12b show the dynamic performance with a 15Hz
signal superimposed on a 2V DC level. The same signal
with no DC level is shown in Figures 12c and 12d.
SERIAL INTERFACE
The LTC2424/LTC2428 transmit the conversion results,
program the channel selection, and receive the start of
conversion command through a synchronous 4-wire in-
terface (SCK = CLK, CSADC = CSMUX). During the conver-
sion and sleep states, this interface can be used to assess
the converter status. While in the sleep state this interface
may be used to program an input channel. During the data
output state, it is used to read the conversion result.
ADC Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 25) is used to
synchronize the data transfer. Each bit of data is shifted out
of the SDO pin on the falling edge of the serial clock.
REFERENCE VOLTAGE (V)
1.0
TOTAL UNADJUSTED ERROR (ppm)
128
192
5.0
24248 F08
64
0
2.0
3.0
4.0
1.5
2.5
3.5
4.5
256
96
160
32
224
OUTPUT RATE = 100sps
12 BITS
13 BITS
14 BITS
15 BITS
Figure 8. Total Error vs V
REF
(Output Rate = 100sps)
INPUT VOLTAGE (V)
0
–40
TOTAL UNADJUSTED ERROR (ppm)
–30
–25
–20
–15
–10
–5
24248 F09
0
5
10
–35
2.5
V
CC
= 5V
V
REF
= 2.5V
Figure 9. Total Unadjusted Error at
100 Samples/Second (No Averaging)
INPUT VOLTAGE (V)
0
TOTAL UNADJUSTED ERROR (ppm)
–2
0
2
5
24248 F10
–4
–6
–10
–8
6
4
V
CC
= 5V
V
REF
= 5V
Figure 10. Total Unadjusted Error at
7.5 Samples/Second (No Averaging)
