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74AUP2G240GF,115
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P26
74AUP2G240
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2013. All rights rese
rved.
Product data sheet
Rev
. 8 — 24 Janu
ary 2013
15 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buf
fer/line driver; 3-st
ate
13. Package
outline
Fig 10.
Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
L
H
E
L
p
wy
v
ce
D
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8
°
0
°
0.13
0.1
0.2
0.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1
MO-187
02-06-07
w
M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v
M
A
X
A
y
2.5
5 mm
0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index
74AUP2G240
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2013. All rights rese
rved.
Product data sheet
Rev
. 8 — 24 Janu
ary 2013
16 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buf
fer/line driver; 3-st
ate
Fig 1
1.
Package outline
SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
SOT833-1
- - -
MO-252
- - -
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e
1
e
A
1
b
L
L
1
e
1
e
1
0
1
2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm
0.25
0.17
2.0
1.9
0.35
0.27
A
1
max
b
E
1.05
0.95
D
ee
1
L
0.40
0.32
L
1
0.5
0.6
A
(1)
max
0.5
0.04
1
8
2
7
3
6
4
5
8
×
(2)
4
×
(2)
A
74AUP2G240
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2013. All rights rese
rved.
Product data sheet
Rev
. 8 — 24 Janu
ary 2013
17 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buf
fer/line driver; 3-st
ate
Fig 12.
Package
outline SOT1089 (XSON
8)
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
SOT1089
MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm
max
nom
min
0.5
0.04
1.40
1.35
1.30
1.05
1.00
0.95
0.55
0.35
0.35
0.30
0.27
A
(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
A
1
bL
1
0.40
0.35
0.32
0.20
0.15
0.12
DE
e
e
1
L
0
0.5
1 mm
scale
terminal 1
index area
E
D
detail X
A
A
1
L
L
1
b
e
1
e
terminal 1
index area
1
4
8
5
(4
×
)
(2)
(8
×
)
(2)
X
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P26
74AUP2G240GF,115
Mfr. #:
Buy 74AUP2G240GF,115
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers Low-Power dual inverting buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL
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Ups
TNT
EMS
Payment:
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