74AUP2G240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 3 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aah782
1A
2Y
1Y
1OE
2A
2OE
EN
EN
001aah783
Fig 3. Pin configuration SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G240
1OE V
CC
1A 2OE
2Y 1Y
GND 2A
001aaf407
1
2
3
4
6
5
8
7
74AUP2G240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 4 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-2
001aaj919
74AUP2G240
Transparent top view
8
7
6
5
1
2
3
4
1OE
1A
2Y
GND
V
CC
2OE
1Y
2A
001aaf409
1A1Y
1OE
V
CC
2Y
2OE
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74AUP2G240
Table 3. Pin description
Symbol Pin Description
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
SOT902-2
1OE
, 2OE 1, 7 7, 1 output enable input (active LOW)
1A, 2A 2, 5 6, 3 data input
GND 4 4 ground (0 V)
1Y, 2Y 6, 3 2, 5 data output
V
CC
8 8 supply voltage
Table 4. Function table
[1]
Input Output
nOE nA nY
LLH
LHL
HXZ
74AUP2G240 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 5 of 25
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 C the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8 and XQFN8 packages: above 118 C the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
10. Static characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +4.6 V
I
IK
input clamping current V
I
<0V 50 - mA
V
I
input voltage
[1]
0.5 +4.6 V
I
OK
output clamping current V
O
<0V 50 - mA
V
O
output voltage Active mode and Power-down mode
[1]
0.5 +4.6 V
I
O
output current V
O
=0 VtoV
CC
- 20 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[2]
-250mW
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.8 3.6 V
V
I
input voltage 0 3.6 V
V
O
output voltage Active mode 0 V
CC
V
Power-down mode; V
CC
=0V 0 3.6 V
T
amb
ambient temperature 40 +125 C
t/V input transition rise and fall rate V
CC
= 0.8 V to 3.6 V 0 200 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
T
amb
= 25 C
V
IH
HIGH-level input voltage V
CC
= 0.8 V 0.70 V
CC
-- V
V
CC
= 0.9 V to 1.95 V 0.65 V
CC
-- V
V
CC
= 2.3 V to 2.7 V 1.6 - - V
V
CC
= 3.0 V to 3.6 V 2.0 - - V
V
IL
LOW-level input voltage V
CC
= 0.8 V - - 0.30 V
CC
V
V
CC
= 0.9 V to 1.95 V - - 0.35 V
CC
V
V
CC
= 2.3 V to 2.7 V - - 0.7 V
V
CC
= 3.0 V to 3.6 V - - 0.9 V

74AUP2G240GF,115

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers Low-Power dual inverting buffer
Lifecycle:
New from this manufacturer.
Delivery:
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