P3PS850BHG-08CR

P3PS850BH
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10
NOTE: Refer Pin Description table for Functionality details.
Analog Deviation Control
CLKIN
GND
V
DD
2.2 mFC2
ModOUT
ModOUT Clock
P3PS850BH
Frequency Selection
Control
V
DD
0.1 mF
CLKIN
R
Rs
V
DD
C1
FS
SSEXTR
PD#/OE
Rx
Power down
Control
Modulation Rate
Control
V
DD
VDDIN
Recommended Noise
reduction Filter
MR
Figure 26. Typical Application Schematic
5
7
6
8
4
1
2
3
P3PS850BH
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11
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
Dedicated V
DD
and GND planes.
The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the V
DD
pin as possible. No vias should be used between the
decoupling capacitor and V
DD
pin. The PCB trace to V
DD
pin and the ground via should be kept as short as possible.
All the V
DD
pins should have decoupling capacitors.
In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in Figure 27.
As short as
possible
VDD
GND
CLKIN
FS
SSEXTR
PD#/OE
Modout
GND
MR
As short as
possible
R
Rs
Figure 27.
ORDERING INFORMATION
Part Number
Top
Marking
Temperature Package Type Shipping
P3PS850BHG08CR DG 20°C to +85°C 8Pin (2 mm x 2 mm) WDFN(TDFN)
(PbFree)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates PbFree.
P3PS850BH
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12
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
C
A
SEATING
PLANE
D
E
0.10 C
A3
A
A1
0.10 C
DIM
A
MIN
MILLIMETERS
0.70
A1 0.00
A3 0.20 REF
b 0.20
D 2.00 BSC
E 2.00 BSC
e 0.50 BSC
PIN ONE
REFERENCE
0.05 C
0.05 C
8X
A0.10 C
NOTE 3
L
e
b
B
4
5
8X
1
8
0.05 C
0.50
L
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.78
7X
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
0.35
PITCH
8X
0.80
0.05
0.30
0.60
MAX
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
---
L1
0.15
B
TOP VIEW
SIDE VIEW
e/2
1
PACKAGE
OUTLINE
DETAIL B
DETAIL A
2X
2X
8X
RECOMMENDED
0.88
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
P3PS850BH/D
TimingSafe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81358171050
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative

P3PS850BHG-08CR

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL 18-72MHZ 2.5V/3.3V TS EMI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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