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ISL6530CR-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
FN9052.2
November 15, 2004
Typical Application
BOOT1
R
FB2
+5V
+5V
RESET
V
REF
(.5xV
DDQ
)
UGATE1
PHASE1
PVCC1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
PGND2
PGND1
COMP2
FB2
SENSE2
SENSE1
FB1
COMP1
OCSET/SD
PGOOD
VCC
GNDA
V2_SD
VREF_IN
VREF
SLEEP
R
FB1
C
OUT2
L
OUT2
C
OUT1
L
OUT1
Q
1
Q
2
Q
3
Q
4
D
BOOT1
D
BOOT2
C
BOOT2
C
BOOT1
R
OCSET
PGOOD
ISL6530
V
DDQ
V
TT
FIGURE 1. TYPICAL APPLICATION FOR ISL6530
ISL6530
5
FN9052.2
November 15, 2004
Absolute Maximum Ratings Thermal Information
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Boot Voltage, V
BOOTn
- V
PHASEn
. . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
Thermal Resistance
JA
(
o
C/W)
JC
(
o
C/W)
SOIC Package (Note 1) . . . . . . . . . . . . 65 N/A
QFN Package (Note 2). . . . . . . . . . . . . 33 4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead tips only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
JC,
the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications Recommended Operating Conditions with Vcc = 5V, Unless Otherwise Noted
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply I
CC
OCSET/SD = V
CC
;
UGATE1, UGATE2, LGATE1, and LGATE2
Open
-5-mA
Shutdown Supply OCSET/SD = 0V - 3 - mA
POWER-ON RESET
Rising V
CC
Threshold V
OCSET/SD
= 4.5V 4.25 - 4.5 V
Falling V
CC
Threshold V
OCSET/SD
= 4.5V 3.75 - 4.0 V
OSCILLATOR
Free Running Frequency V
CC
= 5 275 300 325 kHz
REFERENCES
Reference Voltage
(V2 Error Amp Reference)
V
VREF
SENSE1 = 2.5V 49.5 50 50.5
%SENSE1
V1 Error Amp Reference Voltage
Tolerance
--2
V1 Error Amp Reference V
REF
V
CC
= 5 - 0.8 - V
ERROR AMPLIFIERS
DC Gain -82- dB
Gain-Bandwidth Product GBW - 15 - MHz
Slew Rate SR COMP = 10pF - 6 - V/s
WINDOW REGULATOR
Load Current -±10- mA
Output Voltage Error V2_SD = VCC; ±10mA load on V2 - ±7 %
GATE DRIVERS
Upper Gate Source (UGATE1 and 2) I
UGATE
V
CC
= 5V, V
UGATE
= 2.5V - -1 - A
Upper Gate Sink (UGATE1 and 2) I
UGATE
V
UGATE-PHASE
= 2.5V - 1 - A
Lower Gate Source (LGATE1 and 2) I
LGATE
V
CC
= 5V, V
LGATE
= 2.5V - -1 - A
Lower Gate Sink (LGATE1 and 2) I
LGATE
V
LGATE
= 2.5V - 2 - A
PROTECTION
OCSET/SD Current Source I
OCSET
V
OCSET
= 4.5VDC 34 40 46 A
OCSET/SD Disable Voltage V
RESET
-0.8- V
ISL6530
6
FN9052.2
November 15, 2004
Functional Pin Description
24 LEAD (SOIC)
TOP VIEW
32 LEAD (QFN)
TOP VIEW
BOOT1 and BOOT2
These pins provide bias voltage to the upper MOSFET
drivers. A single capacitor bootstrap circuit may be used to
create a BOOT voltage suitable to drive a standard N-
Channel MOSFET.
UGATE1 and UGATE2
Connect UGATE1 and UGATE2 to the corresponding upper
MOSFET gate. These pins provide the gate drive for the
upper MOSFETs. UGATE2 is also monitored by the adaptive
shoot through protection to determine when the upper FET
of the V
TT
regulator has turned off.
LGATE1 and LGATE2
Connect LGATE1 and LGATE2 to the corresponding lower
MOSFET gate. These pins provide the gate drive for the
lower MOSFETs. These pins are monitored by the adaptive
shoot through protection to determine when the lower FET
has turned off.
PGND1 and PGND2
These are the power ground connections for the gate drivers
of the PWM controllers. Tie these pins to the ground plane
through the lowest impedence connection available.
OCSET/SD
A resistor (R
OCSET
) connected from this pin to the drain of
the upper MOSFET of the V
DDQ
regulator sets the
overcurrent trip point. R
OCSET
, an internal 40A current
source (I
OCS
), and the upper MOSFET on-resistance
(r
DS(ON)
) set the V
DDQ
converter over-current (OC) trip
point according to the following equation:
An overcurrent trip cycles the soft-start function.
Pulling the OCSET/SD pin to ground resets the ISL6530 and
all external MOSFETS are turned off allowing the two output
voltage power rails to float.
PGOOD
A high level on this open-drain output indicates that both the
V
DDQ
and V
TT
regulators are within normal operating
voltage ranges.
GNDA
Signal ground for the IC. Tie this pin to the ground plane
through the lowest impedence connection available.
VCC
The 5V bias supply for the chip is connected to this pin. This
pin is also the positive supply for the lower gate driver,
LGATE2. Connect a well decoupled 5V supply to this pin.
V2_SD
A high level on the V2_SD input places the V2 controller into
“sleep” mode. In sleep mode, both UGATE2 and LGATE2
are driven low, effectively floating the V
TT
supply.
15
16
17
10
9
8
VREF_IN
PHASE2
SENSE2
FB2
VCC
GNDA
18
19
20
21
22
23
24
7
6
5
4
3
2
1
BOOT1
PHASE1
FB1
SENSE1
VREF
PGND1
PVCC1
OCSET/SD
V2_SD
PGOOD
COMP2
LGATE1
COMP1
UGATE1
13
14
12
11
UGATE2
LGATE2
PGND2
BOOT2
BOOT1
BOOT1
UGATE1
UGATE1
PGND1
PGND1
LGATE1
PVCC1
PHASE2
BOOT2
BOOT2
UGATE2
PGND2
PGND2
LGATE2
VCC
PHASE 1
VREF
FB1
COMP1
SENSE1
VREF_IN
GNDA
GNDA
PVCC1
OCSET/SD
V2_SD
PGOOD
COMP2
SENSE2
FB2
VCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
910111213141516
I
PEAK
I
OCS
R
OCSET
r
DS ON
--------------------------------------------=
ISL6530
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ISL6530CR-T

Mfr. #:
Buy ISL6530CR-T
Manufacturer:
Renesas / Intersil
Description:
IC REG CTRLR INTEL 2OUT 32QFN
Lifecycle:
New from this manufacturer.
Delivery:
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