DS1330W
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READ MODE
The DS1330W executes a read cycle whenever
(Write Enable) is inactive (high) and
(Chip
Enable) and
(Output Enable) are active (low). The unique address specified by the 15 address inputs
(A
0
- A
14
) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
and
(Output Enable) access times are also satisfied. If
and
access times are not
satisfied, then data access must be measured from the later-occurring signal (
or
) and the limiting
parameter is either t
CO
for
or t
OE
for
rather than address access.
WRITE MODE
The DS1330W executes a write cycle whenever the
and
signals are in the active (low) state after
address inputs are stable. The later-occurring falling edge of
or
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
or
. All address inputs must
be kept valid throughout the write cycle.
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (
and
active) then
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1330W provides full-functional capability for V
CC
greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V
CC
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V
CC
rises above approximately 2.5 volts, the power
switching circuit connects external V
CC
to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V
CC
exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1330W has the ability to monitor the external V
CC
power supply. When an out-of-tolerance power
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting
. On power-up,
is held active for 200ms nominally to prevent system operation
during power-on transients and to allow t
REC
to elapse.
has an open-drain output driver.
BATTERY MONITORING
The DS1330W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within t
REC
after V
CC
rises above V
TP
and is suspended when power failure
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
is asserted. Once asserted,
remains active until the module is replaced.
The battery is still re-tested after each V
CC
power-up, however, even if
is active. If the battery
voltage is found to be higher than 2.6V during such testing,
is de-asserted and regular 24-hour testing
resumes.
has an open-drain output driver.
