Rev 1.8, March 16 , 2012 Page 4 of 12
SL18860DC
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C
Parameter Symbol Condition Min Typ Max Unit
Input Clock Range
CLKIN External Clock, CMOS square wave 10 26.000 52 MHz
Output Clock Range
CLKOUT
External Clock, CMOS square wave
CLKOUT1/2/3
10 26.000 52 MHz
Input Clock Voltage
Swing Level
VINpp VDD=1.8V 0.72 1 - Vpp
Input Duty Cycle
DCIN CLKIN, Pin 3 30 50 70 %
Output Clock Rise
Time
tr
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
- 2.0 4.00 ns
Output Clock Fall
Time
tf
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
- 2.0 4.00 ns
Additive Phase Noise
APN-1
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
- -140 - dBc/Hz
Additive Phase Noise
APN-2
CLKIN=26MHz and 10 kHz offset
CLKOUT1/2/3
- -150 - dBc/Hz
Additive Phase Noise
APN-3
CLKIN=26MHz and 100 kHz offset
CLKOUT1/2/3
- -159 - dBc/Hz
Power-up Time
tPU
Time duration until CLKOUT1/2/3
frequency reaches valid frequency
after power supply reaches 0.9xVDD
value
- 100 200 Ns
Output Enable Time
tOE1
Time from OE raising edge to active
at outputs CLKOUT1/2/3
(Asynchronous)
- 25 - ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs CLKOUT1/2/3
(Asynchronous)
- 25 - ns
Output Enable Time
tOE2
Active recovery time from standby
(CLKIN=0 or 1) to active at outputs
CLKOUT1/2/3
- 100 - Ns
Rev 1.8, March 16 , 2012 Page 1 of 12
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SL18860DC
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Description Symbol Condition Min Typ Max Unit
Operating Voltage
VDD Operation range, 2.5V+/-10% 2.25 2.50 2.75 V
Operating Temperature
TA I-Grade -40 25 85 ºC
Input Low Voltage
VIL CMOS Level, Pins 3,5, 6 and 7 VSS - 0.3VDD V
Input High Voltage
VIH CMOS Level, Pins 3,5, 6 and 7 0.7VDD - VDD V
Output High Voltage
VOH IOH=-4mA , Pins 4, 8, 9 and 10 VDD-0.4 - - V
Output Low Voltage
VOL IOL=-4mA, Pins 4, 8, 9 and 10 - - 0.4 V
Input Leakage Current
ILH VIN=VDD, Pins 5, 6 and 7 -30 - 30 μA
Input Leakage Current
ILL VIN=GND, Pins 5, 6 and 7 -15 - 15 μA
Pull-Down Resistor
RPD Pins 5, 6 and 7 100 150 250
Operating Supply Current
IDD1
CLKIN=26MHz,
OE1=OE2=OE3=1
- 3.0 - mA
Operating Supply Current
IDD2
OE1=OE2=OE3=0
CLKIN=Low or High
- - 1.5 µA
Input Capacitance
CIN Pins 5, 6 and 7 - 3 5 pF
Load Capacitance
CL CLKOUT1/2/3, Pins 8, 9 and 10 - 10 20 pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Parameter Symbol Condition Min Typ Max Unit
Input Clock Range
CLKIN External Clock, CMOS square wave 10 26.000 52 MHz
Output Clock Range
CLKOUT
External Clock, CMOS square wave
CLKOUT1/2/3
10 26.000 52 MHz
Input Clock Voltage
Swing Level
VINpp
VDD=2.5V, connect to CLKIN directly 1.0 1.2 - V
VDD=2.5V, connect to CLKIN through
AC coupling and bias circuit
0.6 - - V
Input Duty Cycle
DCIN CLKIN, Pin 3 30 50 70 %
Output Clock Rise
Time
tr
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
- 2.0 4.00 ns
Output Clock Fall
Time
tf
VDD=1.8, CL=10pF, measured from
10 to 90% of VDD, Pins 4, 8, 9 and
10
- 2.0 4.00 ns
Additive Phase Noise
APN-1
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
- -142 - dBc/Hz
Rev 1.8, March 16 , 2012 Page 2 of 12
SL18860DC
Additive Phase Noise
APN-2
CLKIN=26MHz and 10 kHz offset
CLKOUT1/2/3
- -156 - dBc/Hz
Additive Phase Noise
APN-3
CLKIN=26MHz and 100 kHz offset
CLKOUT1/2/3
- -164 - dBc/Hz
Power-up Time
tPU
Time for CLKOUT1/2/3 frequency to
reach valid frequency after power
supply reaches 0.9xVDDvalue
- 100 200 ns
Output Enable Time
tOE1
Time from OE raising edge to active
at outputs CLKOUT1/2/3
(Asynchronous)
- 25 - ns
Output Disable Time
tOD
Time from OE falling edge to Hi-Z at
outputs CLKOUT1/2/3
(Asynchronous)
- 25 - ns
Output Enable Time
tOE2
Active recovery time from standby
(CLKIN=0 or 1) to active at outputs
CLKOUT1/2/3
- 100 - ns
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10% and Operation Temperature Range -40 to +85°C
Description Symbol Condition Min Typ Max Unit
Operating Voltage
VDD Operation range , 3.3V+/-10% 2.95 3.3 3.65 V
Operating Temperature
TA I-Grade -40 25 85 ºC
Input Low Voltage
VIL CMOS Level, Pins 3.5, 6 and 7 VSS - 0.3VDD V
Input High Voltage
VIH CMOS Level, Pins 3.5, 6 and 7 0.7VDD - VDD V
Output High Voltage
VOH IOH=-4mA , Pins 4, 8, 9 and 10 VDD-0.4 - - V
Output Low Voltage
VOL IOL=-4mA, Pins 4, 8, 9 and 10 - - 0.5 V
Input Leakage Current
ILH VIN=VDD, Pins 5, 6 and 7 -35 - 35 μA
Input Leakage Current
ILL VIN=GND, Pins 5, 6 and 7 -20 - 20 μA
Pull-Down Resistor
RPD Pins 5, 6 and 7 100 150 250
Operating Supply Current
IDD1
CLKIN=26MHz,
OE1=OE2=OE3=1
- 3.4 - mA
Operating Supply Current
IDD2
OE1=OE2=OE3=0
CLKIN=Low or High
- - 2.0 µA
Input Capacitance
CIN Pins 5, 6 and 7 - 3 5 pF
Load Capacitance
CL CLKOUT1/2/3, Pins 8, 9 and 10 - 10 25 pF

SL18860DCT

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Buffer Low phase jitter, TCXO distribution buffer
Lifecycle:
New from this manufacturer.
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