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XA2C384-10TQG144I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
DS556 (v1.1) May 5, 2007 www.xilinx.com 1
Product Specification
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
• Guaranteed to meet full electrical specifications over
T
A
= -40° C to +105° C with T
J
Maximum = +125° C
(Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in the following package option
- 144-pin TQFP with 118 user I/O
- Pb-free only for this package
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- Hot pluggable
Refer to the CoolRunner™-II Automotive CPLD family data
sheet for architecture description.
WARNING: Programming temperature range of
T
A
= 0° C to +70° C.
Description
The CoolRunner-II Automotive 384-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
This device consists of twenty four Function Blocks
inter-connected by a low power Advanced Interconnect
Matrix (AIM). The AIM feeds 40 true and complement inputs
to each Function Block. The Function Blocks consist of a 40
by 56 P-term PLA and 16 macrocells which contain numer-
ous configuration bits that allow for combinational or regis-
tered modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
0
XA2C384 CoolRunner-II
Automotive CPLD
DS556 (v1.1) May 5, 2007
00
Product Specification
R
XA2C384 CoolRunner-II Automotive CPLD
2 www.xilinx.com DS556 (v1.1) May 5, 2007
Product Specification
R
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Four I/O banks are available on the CoolRunner-II
Automotive 384 macrocell device that permit easy interfac-
ing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II Automotive 384-macrocell CPLD is I/O
compatible with various I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II Auto-
motive CPLDs employ RealDigital a design technique that
makes use of CMOS technology in both the fabrication and
design methodology. RealDigital design technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high-performance and low power
operation.
Supported I/O Standards
The CoolRunner-II Automotive 384-macrocell device fea-
tures LVCMOS and LVTTL I/O implementations. See
Table 1 for I/O standard voltages. The LVTTL I/O standard
is a general purpose EIA/JEDEC standard for 3.3V applica-
tions that use an LVTTL input buffer and Push-Pull output
buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V
applications. CoolRunner-II Automotive CPLDs are also
1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XA2C384
IOSTANDARD Attribute Output V
CCIO
Input V
CCIO
LVTTL 3.3 3.3
LVCMOS33 3.3 3.3
LVCMOS25 2.5 2.5
LVCMOS18 1.8 1.8
LVCMOS15
(1)
1.5 1.5
(1) LVCMOS15 requires Schmitt-trigger inputs.
Figure 1: I
CC
vs Frequency
Table 2: I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
0 255075100125
Typical I
CC
(mA) 0.023 17.5 35.03 52.53 70.03 87.53
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
Frequency (MHz)
DS556_01_092106
I
CC
(mA)
0
0
50
100
10025 75
125
50
XA2C384 CoolRunner-II Automotive CPLD
DS556 (v1.1) May 5, 2007 www.xilinx.com 3
Product Specification
R
Recommended Operating Conditions
DC Electrical Characteristics
(Over Recommended Operating Conditions)
Absolute Maximum Ratings
(1)
Symbol Description Value Units
V
CC
Supply voltage relative to ground –0.5 to 2.0 V
V
CCIO
Supply voltage for output drivers –0.5 to 4.0 V
V
JTAG
(2)
JTAG input voltage limits –0.5 to 4.0 V
V
CCAUX
JTAG input supply voltage –0.5 to 4.0 V
V
IN
(1)
Input voltage relative to ground –0.5 to 4.0 V
V
TS
(1)
Voltage applied to 3-state output –0.5 to 4.0 V
T
STG
(3)
Storage Temperature (ambient) –65 to +150 °C
T
J
Junction Temperature +125 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging
information on the Xilinx website. For Pb-free
packages, see XAPP427.
Symbol Parameter Min Max Units
V
CC
Supply voltage for internal logic
and input buffers
Industrial T
A
= –40°C to +85°C 1.7 1.9 V
Q-Grade T
A
= -40° C to +105° C
T
J
Maximum = +125° C
1.7 1.9 V
V
CCIO
Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V
V
CCAUX
Supply voltage for JTAG programming 1.7 3.6 V
Symbol Parameter Test Conditions Typical Max. Units
I
CCSB
Standby current Industrial V
CC
= 1.9V, V
CCIO
= 3.6V 79 350 μA
I
CCSB
Standby current Q-grade V
CC
= 1.9V, V
CCIO
= 3.6V 79 4.0 mA
I
CC
(1)
Dynamic current f = 1 MHz 6.0 mA
f = 50 MHz 50 mA
C
JTAG
JTAG input capacitance f = 1 MHz - 10 pF
C
CLK
Global clock input capacitance f = 1 MHz - 12 pF
C
IO
I/O capacitance f = 1 MHz - 10 pF
I
IL
(2)
Input leakage current V
IN
= 0V or V
CCIO
to 3.9V - +/–10 μA
I
IH
(2)
I/O High-Z leakage V
IN
= 0V or V
CCIO
to 3.9V - +/–10 μA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

XA2C384-10TQG144I

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Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices
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