XA2C384 CoolRunner-II Automotive CPLD
6 www.xilinx.com DS556 (v1.1) May 5, 2007
Product Specification
R
AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter
-10 -11
UnitsMin. Max. Min. Max.
T
PD1
Propagation delay single p-term - 9.2 - 9.2 ns
T
PD2
Propagation delay OR array - 10.0 - 10.0 ns
T
SUD
Direct input register set-up time 4.2 - 4.5 - ns
T
SU1
Setup time fast (single p-term) 3.3 - 3.8 - ns
T
SU2
Setup time (OR array) 4.1 - 4.6 - ns
T
HD
Direct input register hold time 0.0 - 0.0 - ns
T
H
Hold time (OR array or p-term) 0.0 - 0.3 - ns
T
CO
Clock to output - 7.9 - 7.9 ns
F
TOGGLE
(1)
Internal toggle rate - 166 - 166 MHz
F
SYSTEM1
(2)
Maximum system frequency - 125 - 118 MHz
F
SYSTEM2
(2)
Maximum system frequency - 114 - 108 MHz
F
EXT1
(3)
Maximum external frequency - 89 - 85 MHz
F
EXT2
(3)
Maximum external frequency - 83 - 80 MHz
T
PSUD
Direct input register p-term clock setup time 2.5 - 2.7 - ns
T
PSU1
P-term clock setup time (single p-term) 1.9 - 2.1 - ns
T
PSU2
P-term clock setup time (OR array) 2.7 - 2.9 - ns
T
PHD
Direct input register p-term clock hold time 0.4 - 1.2 - ns
T
PH
P-term clock hold 1.3 - 1.7 - ns
T
PCO
P-term clock to output - 9.3 - 9.3 ns
T
OE
/T
OD
Global OE to output enable/disable - 9.2 - 9.2 ns
T
POE
/T
POD
P-term OE to output enable/disable - 10.2 - 10.4 ns
T
MOE
/T
MOD
Macrocell driven OE to output enable/disable - 12.5 - 12.5 ns
T
PAO
P-term set/reset to output valid - 11.6 - 11.6 ns
T
AO
Global set/reset to output valid - 11.5 - 11.5 ns
T
SUEC
Register clock enable setup time 3.4 - 4.0 - ns
T
HEC
Register clock enable hold time 0.0 - 0.3 - ns
T
CW
Global clock pulse width High or Low 3.0 - 3.0 - ns
T
PCW
P-term pulse width High or Low 10.0 - 10.0 - ns
T
APRPW
Asynchronous preset/reset pulse width (High or Low) 10.0 - 10.0 - ns
T
DGSU
Set-up before DataGATE latch assertion 0.0 - 0.0 - ns
T
DGH
Hold to DataGATE latch assertion 6.0 - 6.0 - ns
T
DGR
DataGATE recovery to new data 11.0 11.0 ns
T
DGW
DataGATE low pulse width 5.0 - 5.0 - ns
T
CDRSU
CDRST setup time before falling edge GCLK2 2.5 - 2.5 - ns
T
CDRH
CDRST hold time before falling edge GCLK2 0.0 - 0.2 - ns
T
CONFIG
Configuration time - 200 - 200 μs
Notes:
1. F
TOGGLE
is the maximum frequency of a T flip-flop can reliably toggle (see CoolRunner-II Automotive CPLD family data sheet).
2. F
SYSTEM1
(1/T
CYCLE
) is the internal operating frequency for a device with 16-bit Resetable binary counter through one p-term per
macrocell while F
SYSTEM2
is through the OR array (one counter per function block)
3. F
EXT1
(1/T
SU1
+T
CO
) is the maximum external frequency using one p-term while F
EXT2
is through the OR array
4. Typical configuration current during
T
CONFIG
is 25 mA.
