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FEATURES
3V or 5V Operation
Ultra-Low Power Consumption
Two Digitally Controlled, 256-Position
Potentiometers
14-Pin TSSOP (173 mil) and 16-Pin SO (150
mil) Packaging Available for Surface-Mount
Applications
Addressable Using 3 Address Inputs
2-Wire Serial Interface
Operating Temperature Range:
- Industrial: -40°C to +85°C
Standard Resistance Values:
- DS1803-010 10kΩ
- DS1803-050 50kΩ
- DS1803-100 100kΩ
PIN ASSIGNMENT
PIN DESCRIPTION
L0, L1 - Low End of Resistor
H0, H1 - High End of Resistor
W0,W1 - Wiper terminal of Resistor
V
CC
- 3V/5V Power Supply Input
A0, A1, A2 - Chip Select Inputs
SDA - Serial Data I/O
SCL - Serial Clock Input
GND - Ground
NC - No Connection
DESCRIPTION
The DS1803 addressable dual digital potentiometer features two independently controlled 256-position
potentiometers. Device control is achieved through a 2-wire serial interface. Three address pins allow up
to 8 DS1803’s to share the same 2-wire interface. The exact wiper position of each potentiometer can be
written or read. The DS1803 is available in a 16-pin DIP, 16-pin SO, and 14-pin TSSOP package. The
device is available in three standard resistance values: 10k, 50k, and 100k and is specified over the
industrial temperature range.
DS1803
Addressable Dual Digital Potentiomete
r
www.maxim-ic.com
H1 1 14 VCC
L1 2 13 NC
W1 3 12 H0
A2 4 11 L0
A1 5 10 W0
A0 6 9 SDA
GND 7 8 SCL
DS1803 14-PIN TSSOP (173 MIL)
H1 1 16 VCC
NC 2 15 NC
L1 3 14 H0
W1 4 13 L0
A2 5 12 W0
A1 6 11 NC
A0 7 10 SDA
GND 8 9 SCL
DS1803Z 16-PIN SO (150 MIL)
DS1803 16-PIN DIP (300 MIL)
See Mech. Drawings Section on Website
DS1803
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DEVICE OPERATION
The DS1803 is an addressable, digitally controlled device which has two 256-position potentiometers. A
functional block diagram of the part is shown in Figure 1. Communication and control of the device is
accomplished via a 2-wire serial interface. Address inputs A0, A1, and A2 allow up to 8 DS1803s to
share the same 2-wire interface.
Each potentiometer is composed of a 256 position resistor array. Two 8-bit registers, each assigned to a
respective potentiometer, are used to set the wiper position on the resistor array. The wiper terminal is
multiplexed to one of 256 positions on the resistor array based on its corresponding 8-bit register value.
For example, the high-end terminals, H0 and H1, have wiper position values FFh while the low-end
terminals, L0 and L1, have wiper position values 00h.
The DS1803 is a volatile device that does not maintain the position of the wiper during power-down or
loss of power. On power-up, the DS1803 wipers’ position will be set to position 00h - the low-end
terminals. The user may then set the wiper value to a desired position.
Communication with the DS1803 takes place over the 2-wire serial interface consisting of the bi-
directional pin, SDA, and the serial clock input, SCL. Complete details of the 2-wire interface are
discussed in the section entitled “2-wire Serial Data Bus.”
Application Considerations
The DS1803 is offered in three standard resistor values, which include 10kΩ, 50kΩ, and 100kΩ. The
resolution of the potentiometer is defined as R
TOT
/255, where R
TOT
is the total resistor value of the
potentiometer. The DS1803 is designed to operate using 3V or 5V power supplies over the industrial
(-40°C to +85°C) temperature range. Maximum input signal levels across the potentiometer cannot
exceed the operating power supply of the device.
2-WIRE SERIAL DATA BUS
The DS1803 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data
on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master”. The devices that are controlled by the master are “slaves”. The bus must
be controlled by a master device which generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1803 operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 2).
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
DS1803
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Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/
W * bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1. Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the
master is the control byte (slave address). Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver: The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1803 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1803 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.

DS1803Z-100

Mfr. #:
Manufacturer:
Description:
IC POT DUAL ADDRESS 100K 16-SOIC
Lifecycle:
New from this manufacturer.
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