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NCP3127ADR2G

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NCP3127
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7
General
The NCP3127 is a PWM synchronous buck regulator
intended to supply up to a 2 A load for DC−DC conversion
from 5 V and 12 V buses. The NCP3127 is a regulator that
has integrated high−side and low−side NMOSFETs
switches. The output voltage of the converter can be
precisely regulated down to 800 mV $1.0% when the V
FB
pin is tied to V
OUT
. The switching frequency is internally set
to 350 kHz. A high gain operational transconductance
amplifier (OTA) is used for voltage mode control of the
power stage.
Duty Ratio and Maximum Pulse Width Limits
In steady state DC operation, the duty ratio will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The device can achieve a 75% duty ratio. The
NCP3127 has a preset off−time of approximately 150 ns,
which ensures that the bootstrap supply is charged every
switching cycle. The preset off time does not interfere with
the conversion of 12 V to 0.8 V.
Input Voltage Range (V
IN
and BST)
The input voltage range for both V
IN
and BST is 4.5 V to
13.2 V with referenced to GND and V
SW
. Although BST is
rated at 13.2 V with respect to V
SW
, it can also tolerate
26.5 V with respect to GND.
External Enable/Disable
Once the input voltage has exceeded the boost and UVLO
threshold at 3 V and V
IN
threshold at 4 V, the COMP pin
starts to rise. The V
SW
node is tri−stated until the COMP
voltage exceeds 0.9 V. Once the 0.9 V threshold is exceeded,
the part starts to switch and the part is considered enabled.
When the COMP pin voltage is pulled below the 400 mV
threshold, it disables the PWM logic, the top MOSFET is
driven off, and the bottom MOSFET is driven on. In the
disabled mode, the OTA output source current is reduced to
10 mA.
When disabling the NCP3127 using the COMP / Disable
pin, an open collector or open drain drive should be used as
shown in Figure 16:
COMP
0.9 V
BG
TG
Figure 15. Enable/Disable Driver State Diagram
2N7002E
COMP
Enable
Disable
Gate Signal
COMP
Enable
Disable
Base Signal
MMBT3904
Figure 16. Recommended Disable Circuits
Power Sequencing
Power sequencing can be achieved with NCP3127 using
two general purpose bipolar junction transistors or
MOSFETs. An example of the power sequencing circuit
using the external components is shown in Figure 17.
1.0V
VIN
3.3 V
Figure 17. Power Sequencing
NCP3127
FB1
VSW
COMP
NCP3127
FB1
VSW
COMP
Input Voltage Shutdown Behavior
Input voltage shutdown occurs when the IC stops
switching because the input supply reaches UVLO
threshold. Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VCC
is too low to support the internal rails and power the
converter. For the NCP3127, the UVLO is set to permit
operation when converting from an input voltage of 5 V. If
the UVLO is tripped, switching stops, the internal SS is
discharged, and all MOSFET gates are driven low. The V
SW
node enters a high impedance state and the output capacitors
discharge through the load with no ringing on the output
voltage.
External Soft−Start
The NCP3127 features an external soft−start function,
which reduces inrush current and overshoot of the output
voltage. Soft−start is achieved by using the internal current
NCP3127
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8
source of 10 mA (typ), which charges the external integrator
capacitor of the OTA. Figure 14 is a typical soft−start
sequence. The sequence begins once V
IN
and V
BST
surpass
their UVLO thresholds and OCP programming is complete.
The current sourced out of the COMP pin continually
increases the voltage until regulation is reached. Once the
voltage reaches 400 mV logic is enabled. When the voltage
exceeds 900 mV, switching begins. Current is sourced out of
the COMP pin, placing the regulator into open loop
operation until 800 mV is sensed at the FB pin. Once
800 mV is sensed at the FB pin, open loop operation ends
and closed loop operation begins. In closed loop operation,
the OTA is capable of sourcing and sinking 120 mA.
Figure 18. Soft−Start Sequence
VCC
COMP
VFB
BG
TG
BG Comparator
BG Comparator Output
Vout
UVLO
POR
Delay
Current
COMP
Delay
Soft−Start
Normal Operation
UVLO
0.9 V
3.85 V
4.2 V
DAC Voltage
500 mV
50 mV
Trip Set
Overcurrent Threshold Setting
NCP3127 overcurrent threshold can be set from 50 mV to
550 mV, by adding a resistor (R
SET
) between ISET and
GND. During a short period of time following V
IN
rising
over UVLO threshold, an internal 10 mA current (I
OCSET
) is
sourced from the ISET pin, creating a voltage drop across
R
SET
. The voltage drop is compared against a stepped
internal voltage ramp. Once the internal stepped voltage
reaches the R
SET
voltage, the value is stored internally until
power is cycled. The overall time length for the OC setting
procedure is approximately 9 ms. Connecting an R
SET
resistor between ISET and GND, the programmed threshold
will be:
I
OCth
+
I
OCSET
*R
SET
R
DS(on)
³ 2.0 A +
10 mA*21kW
105 mW
(eq. 1)
I
OCSET
= Sourced current
I
OCth
= Current trip threshold
R
DS(on)
= On resistance of the low side MOSFET
R
SET
= Current set resistor
The R
SET
values range from 5 kW to 55 kW. If R
SET
is not
connected, the device switches the OCP threshold to a fixed
375 mV value (3.57 A), an internal safety clamp on ISET is
triggered as soon as ISET voltage reaches 700 mV, enabling
the 375 mV fixed threshold and ending the OCP setting
period. The current trip threshold tolerance is $25 mV. The
accuracy is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases.
MOSFET tolerances with temperature and input voltage
will vary the over current set threshold operating point. A
graph of the typical current limit set thresholds at 4.5 V and
12 V is shown in Figure 19.
OUTPUT CURRENT (A)
R
SET
(kW)
Figure 19. R
SET
Value for Output Current
5.0 V
12 V
0
0.5
1
1.5
2
2.5
3
3.5
4
5 1015202530
Current Limit Protection
In case of an overload, the low−side (LS) FET will
conduct large currents. The regulator will latch off,
protecting the load and MOSFETs from excessive heat and
damage. Low−side R
DS(on)
sense is implemented at the end
of each LS−FET turn−on duration to sense the current.
While the low side MOSFET is on, the V
SW
voltage is
compared to the user set internally generated OCP trip
voltage. If the V
SW
voltage is lower than OCP trip voltage,
an overcurrent condition occurs and a counter counts
consecutive current trips. If the counter reaches 7, the PWM
logic and both HS−FET and LS−FET are turned off. The
regulator has to go through a Power On Reset (POR) cycle
to reset the OCP fault as shown in Figure 20.
NCP3127
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9
BG
+
−
VOCTH
Current
Flow
0V
VOCTH
PHASE
Low Side
MOSFET
Current
BG
Drive
Figure 20. Current Limit Trip
APPLICATION SECTION
Design Procedure
When starting the design of a buck regulator, it is
important to collect as much information as possible about
the behavior of the input and output before starting the
design.
ON Semiconductor has a Microsoft Excel® based design
tool available online under the design tools section of the
NCP3127 product page. The tool allows you to capture your
design point and optimize the performance of your regulator
based on your design criteria.
Table 4. DESIGN PARAMETERS
Design Parameter Example Value
Input voltage (V
IN
) 10.8 V to 13.2 V
Output voltage (V
OUT
) 3.3 V
Input ripple voltage (V
INRIPPLE
) 300 mV
Output ripple voltage (V
OUTRIPPLE
) 40 mV
Output current rating (I
OUT
) 2 A
Operating frequency (F
SW
) 350 kHz
The buck converter produces input voltage V
IN
pulses that
are LC filtered to produce a lower DC output voltage V
OUT
.
The output voltage can be changed by modifying the on time
relative to the switching period T or switching frequency.
The ratio of high side switch on time to the switching period
is called duty ratio D. Duty ratio can also be calculated using
V
OUT
, V
IN
, the Low Side Switch Voltage Drop V
LSD
, and
the High Side Switch Voltage Drop V
HSD
.
F
SW
+
1
T
(eq. 2)
D +
T
ON
T
and (1 * D) +
T
OFF
T
(eq. 3)
D +
V
OUT
) V
LSD
V
IN
* V
HSD
) V
LSD
[ D +
V
OUT
V
IN
³ 27.5% +
3.3 V
12 V
(eq. 4)
D = Duty cycle
F
SW
= Switching frequency
T = Switching period
T
OFF
= High side switch off time
T
ON
= High side switch on time
V
HSD
= High side switch voltage drop
V
IN
= Input voltage
V
LSD
= Low side switch voltage drop
V
OUT
= Output voltage
Inductor Selection
When selecting an inductor, the designer can employ a
rule of thumb for the design where the percentage of ripple
current in the inductor should be between 10% and 40%.
When using ceramic output capacitors, the ripple current can
be greater because the ESR of the output capacitor is smaller,
thus a user might select a higher ripple current. However,
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NCP3127ADR2G

Mfr. #:
Buy NCP3127ADR2G
Manufacturer:
ON Semiconductor
Description:
Voltage Regulators - Switching Regulators 2A PWM Switching Buck Regulato
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