LTC3809
6
3809fc
PIN FUNCTIONS
PLLLPF (Pin 1): Frequency Set/PLL Lowpass Filter. When
synchronizing to an external clock, this pin serves as the
lowpass fi lter point for the phase-locked loop. Normally,
a series RC is connected between this pin and ground.
W h e n n o t s y n c h r o n i z i n g t o a n e x t e r n a l c l o c k , t h i s p i n s e r v e s
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to V
IN
selects 750kHz
operation. Floating this pin selects 550kHz operation.
Connect a 2.2nF capacitor between this pin and GND, and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
SYNC/MODE (Pin 2): This pin performs four functions:
1) auxiliary winding feedback input, 2) external clock
synchronization input for phase-locked loop, 3) Burst
Mode, pulse-skipping or forced continuous mode select,
and 4) enable spread spectrum modulation operation in
pulse-skipping mode. Applying a clock with frequency
between 250kHz to 750kHz causes the internal oscillator
to phase-lock to the external clock and disables Burst
Mode operation but allows pulse-skipping at low load
currents.
To select Burst Mode operation at light loads, tie this
pin to V
IN
. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
Tying this pin to V
FB
selects pulse-skipping mode. In these
cases, the frequency of the internal oscillator is set by the
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to V
IN
– 0.5V enables spread spectrum modulation
o p e r a t i o n . I n t h i s c a s e , a n i n t e r n a l 2 . 6 μ A p u l l - d o w n c u r r e n t
source helps to set the voltage at this pin by tying a resistor
with appropriate value between this pin and V
IN
. Do not
leave this pin fl oating.
V
FB
(Pin 3): Feedback Pin. This pin receives the remotely
sensed feedback voltage for the controller from an external
resistor divider across the output.
ITH (Pin 4): Current Threshold and Error Amplifi er
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
RUN (Pin 5): Run Control Input. Forcing this pin below
1.1V shuts down the chip. Driving this pin to V
IN
or releas-
ing this pin enables the chip to start-up with the internal
soft-start.
IPRG (Pin 6): Three-State Pin to Select Maximum Peak
Sense Voltage Threshold. This pin selects the maximum
allowed voltage drop between the V
IN
and SW pins (i.e.,
the maximum allowed drop across the external P-channel
MOSFET). Tie to V
IN
, GND or fl oat to select 204mV, 85mV
or 125mV respectively.
BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin
drives the gate of the external N-channel MOSFET. This
pin has an output swing from PGND to V
IN
.
TG (Pin 8): Top (PMOS) Gate Drive Output. This pin drives
the gate of the external P-channel MOSFET. This pin has
an output swing from PGND to V
IN
.
V
IN
(Pin 9): Chip Signal Power Supply. This pin powers
the entire chip, the gate drivers and serves as the positive
input to the differential current comparator.
SW (Pin 10): Switch Node Connection to Inductor. This
pin is also the negative input to the differential current
comparator and an input to the reverse current comparator.
Normally this pin is connected to the drain of the external
P-channel MOSFET, the drain of the external N-channel
MOSFET and the inductor.
GND (Pin 11): Exposed Pad. The Exposed Pad is ground
and must be soldered to the PCB ground for electrical
contact and optimum thermal performance.
