NCL30001
www.onsemi.com
22
AC COMP
AC error
amplifier
gm
+
+
37.33kW
+
VDD
21.33kW
x 4
2.8V
+
To PWM
comparator
g
m
= 100mS
Figure 53. AC EA Buffer Amplifier
V
AC_REF
R
IAVG
I
AVG
R
AC_COMP
I
ACEA(out)
I
ACEA(out)
+
ǒ
2.8 * V
ACEA
37.33k
Ǔ
@ 4
(eq. 1)
The voltage at the PWM non-inverting input is
determined by I
ACEA(out)
, the instantaneous switch current
along and the ramp compensation current. DRV is
terminated once the voltage at the PWM non-inverting input
reaches 4 V.
Current Sense Amplifier
A voltage proportional to the main switch current is
applied to the current sense input, IS
POS
. The current sense
amplifier is a wide bandwidth amplifier with a differential
input. The current sense amplifier has two outputs, PWM
Output and I
AV G
Output. The PWM Output is the
instantaneous switch current which is filtered by the internal
leading edge blanking (LEB) circuitry prior to applying it to
the PWM Comparator non inverting input. The second
output is a filtered current signal resembling the average
value of the input current. Figure 54 shows the internal
architecture of the current sense amplifier.
NCL30001
www.onsemi.com
23
+
t
LEB
blanking
Inst. current
Current sense
amplifier
g
m
= 250mS
To PWM
comparator
To AC error
amplifier
Figure 54. Current Sense Amplifier
V
IAVG
R
IAVG
R
CS
g
m
I
AVG
I
spos
I
p
C
IAVG
Caution should be exercised when designing a filter
between the current sense resistor and the IS
POS
input, due
to the low impedance of this amplifier. Any series resistance
due to a filter creates a voltage offset (V
OS
) due to its input
bias current, CA
Ibias
. The input bias current is typically
60 mA. The voltage offset is given by Equation 2.
V
OS
+ CA
Ibias
@ R
external
(eq. 2)
The offset adds a positive offset to the current sense signal.
The ac error amplifier will then try to compensate for the
average output current which appears never to go to zero and
cause additional zero crossing distortion.
A voltage proportional to the main switch current is
applied to the IS
POS
pin. The IS
POS
pin voltage is converted
into a current, i
1
, and internally mirrored. Two internal
currents are generated, I
CS
and I
AV G
. I
CS
is a high frequency
signal which is a replica of the instantaneous switch current.
I
AV G
is a low frequency signal. The relationship between
V
ISPOS
and I
CS
and I
AV G
is given by Equation 3.
I
CS
+ I
IN
+
V
ISPOS
4k
(eq. 3)
The PWM Output delivers current to the positive input of
the PWM input where it is added to the AC EA and ramp
compensation signal.
The I
AV G
Output generates a voltage signal to a buffer
amplifier. This voltage signal is the product of I
AV G
and an
external R
IAVG
resistor filtered by the capacitor on the I
AV G
pin, C
IAVG
. The pole frequency, f
P
, set by C
IAVG
should be
significantly below the switching frequency to remove the
high frequency content. But, high enough to not to cause
significant distortion to the input full wave rectified
sinewave waveform. A properly filtered average current
signal has twice the line frequency. Equation 4 shows the
relationship between C
IAVG
(in nF) and f
P
(in kHz).
C
IAVG
+
1
2 @ p @ R
IAVG
@ f
P
(eq. 4)
NCL30001
www.onsemi.com
24
The gain of the low frequency current buffer is set by the
resistor at the I
AV G
pin, R
IAVG
. R
IAVG
sets the scaling factor
between the primary peak and primary average currents.
The gain of the current sense amplifier, A
CA
, is given by
Equation 5.
A
CA
+
RI
AVG
4k
(eq. 5)
The current sense signal is prone to leading edge spikes
during the switch turn on due to parasitic capacitance and
inductance. This spike may cause incorrect operation of the
PWM Comparator. The NCL30001 incorporates LEB
circuitry to block the first 200 ns (typical) of each current
pulse. This removes the leading edge spikes without filtering
the current signal waveform.
Oscillator
The oscillator controls the switching frequency, f, the jitter
frequency and the gain of the multiplier. The oscillator ramp
is generated by charging the timing capacitor on the CT Pin,
C
T
, with a 200 mA current source. This current source is
tightly controlled during manufacturing to achieve a
controlled and repeatable oscillator frequency. The current
source turns off and C
T
is immediately discharged with a
pull down transistor once the oscillator ramp reaches its peak
voltage, V
CT(peak)
, typically 4.0 V. The pull down transistor
turns off and the charging current source turns on once the
oscillator ramp reaches its valley voltage, V
CT(valley)
.
Figure 55 shows the resulting oscillator ramp and control
circuitry.
+
To PWM
comparator
To PWM skip
comparator
VDD
VDD
x 1.2
4.0 V / 0.1 V
+
+
Oscillator
Figure 55. Oscillator Ramp and Control Circuitry
Ramp Comp
R
RC
C
T
C
T
The relationship between the oscillator frequency in kHz
and timing capacitor in pF is given by Equation 6.
C
T
+
47000
f
(eq. 6)
A low frequency oscillator modulates the switching
frequency, reducing the controller EMI signature and
allowing the use of a smaller EMI filter. The frequency
modulation or jitter is typically ±6.8% of the oscillator
frequency.

NCL30001DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LED Lighting Drivers ANA PFC CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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