ADP3333ARMZ-2.77R7

ADP3333
Rev. B | Page 9 of 12
THEORY OF OPERATION
The ADP3333 anyCAP LDO uses a single control loop for
regulation and reference functions (see Figure 22). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 that is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
INPUT
Q1
ADP3333
COMPENSATION
CAPACITOR
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
FB
GND
g
m
R
L
C
L
PTAT
V
OS
ATTENUATION
(V
BAND GAP
/V
OUT
)
NONINVERTING
WIDEBAND
DRIVER
02615-022
Figure 22. Functional Block Diagram
A very high gain error amplifier is used to control this loop.
The amplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility
on the trade-off of noise sources and leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1/R2 resistor
divider is loaded by the diode, D1, and a second divider
consisting of R3 and R4, the values can be chosen to produce a
temperature stable output. This unique arrangement specifically
corrects for the loading of the divider so that the error resulting
from base current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value required to keep conventional LDOs
stable changes depending on load and temperature. These ESR
limitations make designing with LDOs more difficult because
of their unclear specifications and extreme variations over
temperature.
With the ADP3333 anyCAP LDO, this is no longer true. This
device can be used with virtually any good quality capacitor,
with no constraint on the minimum ESR. Its innovative design
allows the circuit to be stable with just a small 1.0 μF capacitor
on the output. Additional advantages of the pole splitting
scheme include superior line noise rejection and very high
regulator gain, which leads to excellent line and load regulation.
An impressive ±1.8% accuracy is guaranteed over line, load, and
temperature.
Additional features of the circuit include current limit and
thermal shutdown.
ADP3333
Rev. B | Page 10 of 12
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as
low as 1.0 μF is all that is needed for stability. Larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors (ESR
≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON.
Note that the effective capacitance of some capacitor types falls
below the minimum rated value over temperature or with dc
voltage. Ensure that the capacitor provides at least 1.0 μF of
capacitance over temperature and dc bias.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 μF capacitor from the input to
ground reduces the circuit’s sensitivity to printed circuit board
(PCB) layout and input transients. If a larger output capacitor is
necessary, then a larger value input capacitor is also recommended.
OUTPUT CURRENT LIMIT
The ADP3333 is short-circuit protected by limiting the pass
transistors base drive current. The maximum output current is
limited to about 1 A (see Figure 17).
THERMAL OVERLOAD PROTECTION
The ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (that is, high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current is reduced until the die temperature
drops to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the devices power dissipation should be externally
limited so that the junction temperature does not exceed 125°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
P
D
= (V
IN
V
OUT
) I
L
+ (V
IN
) I
GND
where I
L
and I
GND
are the load current and ground current, and
V
IN
and V
OUT
are the input and output voltages, respectively.
Assuming the worst-case operating conditions are I
L
= 300 mA,
I
GND
= 2.0 mA, V
IN
= 4.0 V, and V
OUT
= 3.0 V, the device power
dissipation is
P
D
= (4.0 V − 3.0 V) 300 mA + (4.0 V) 2.0 mA = 308 mW
The package used on the ADP3333 has a thermal resistance of
158°C/W for 4-layer boards. The junction temperature rise
above ambient is approximately equal to
T
JA
= 0.308 W × 158°C/W = 48.7°C
Therefore, to limit the junction temperature to 125°C, the
maximum allowable ambient temperature is
T
A(MAX)
= 125°C − 48.7°C = 76.3°C
SHUTDOWN MODE
Applying a high signal to the shutdown pin,
SD
, or connecting
it to the input pin,
IN
, turns the output on. Pulling the shutdown
pin to 0.3 V or below, or connecting it to ground, turns the
output off. In shutdown mode, the quiescent current is reduced
to less than 1 μA.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards:
Keep the output capacitor as close as possible to the output
and ground pins.
Keep the input capacitor as close as possible to the input
and ground pins.
PCB traces with larger cross sectional areas remove more
heat from the ADP3333. For optimum heat transfer, use
thick copper with wide traces.
Connect the NC pins (Pin 4, Pin 5, Pin 6, and Pin 8) to
ground for better thermal performance.
The thermal resistance can be decreased by approximately
10% by adding a few square centimeters of copper area to
the lands connected to the pins of the LDO.
Use additional copper layers or planes to reduce the
thermal resistance. Again, connecting the other layers to
the GND and NC pins of the ADP3333 is best, but not
necessary. When connecting the ground pad to other
layers, use multiple vias.
ADP3333
Rev. B | Page 11 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 23. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Output Voltage (V) Package Description Package Option Branding
ADP3333ARM-1.5-RL −40°C to +85°C 1.5 8-Lead MSOP RM-8 LKA
ADP3333ARM-1.5-RL7 −40°C to +85°C 1.5 8-Lead MSOP RM-8 LKA
ADP3333ARM-1.8-RL −40°C to +85°C 1.8 8-Lead MSOP RM-8 LKB
ADP3333ARM-1.8-RL7 −40°C to +85°C 1.8 8-Lead MSOP RM-8 LKB
ADP3333ARM-2.5-RL −40°C to +85°C 2.5 8-Lead MSOP RM-8 LKC
ADP3333ARM-2.5-RL7 −40°C to +85°C 2.5 8-Lead MSOP RM-8 LKC
ADP3333ARM-2.77-RL −40°C to +85°C 2.77 8-Lead MSOP RM-8 LKD
ADP3333ARM-2.77-R7 40°C to +85°C 2.77 8-Lead MSOP RM-8 LKD
ADP3333ARM-3-REEL −40°C to +85°C 3 8-Lead MSOP RM-8 LKE
ADP3333ARM-3-REEL7 −40°C to +85°C 3 8-Lead MSOP RM-8 LKE
ADP3333ARM-3.15-RL −40°C to +85°C 3.15 8-Lead MSOP RM-8 LKF
ADP3333ARM-3.15-R7 40°C to +85°C 3.15 8-Lead MSOP RM-8 LKF
ADP3333ARM-3.3-RL −40°C to +85°C 3.3 8-Lead MSOP RM-8 LKG
ADP3333ARM-3.3-RL7 −40°C to +85°C 3.3 8-Lead MSOP RM-8 LKG
ADP3333ARM-5-REEL −40°C to +85°C 5 8-Lead MSOP RM-8 LKH
ADP3333ARM-5-REEL7 −40°C to +85°C 5 8-Lead MSOP RM-8 LKH
ADP3333ARMZ-1.5-R7
1
−40°C to +85°C 1.5 8-Lead MSOP RM-8 L1X
ADP3333ARMZ-1.5-RL
1
−40°C to +85°C 1.5 8-Lead MSOP RM-8 L1X
ADP3333ARMZ-1.8-RL
1
−40°C to +85°C 1.8 8-Lead MSOP RM-8 L1U
ADP3333ARMZ-1.8RL7
1
−40°C to +85°C 1.8 8-Lead MSOP RM-8 L1U
ADP3333ARMZ-2.5-RL
1
−40°C to +85°C 2.5 8-Lead MSOP RM-8 L1V
ADP3333ARMZ-2.5-R7
1
−40°C to +85°C 2.5 8-Lead MSOP RM-8 L1V
ADP3333ARMZ-2.77R7
1
−40°C to +85°C 2.77 8-Lead MSOP RM-8 L1Y
ADP3333ARMZ-3-R7
1
−40°C to +85°C 3.0 8-Lead MSOP RM-8 L1W
ADP3333ARMZ-3.15R7
1
−40°C to +85°C 3.15 8-Lead MSOP RM-8 L1Z
ADP3333ARMZ-3.3-R7
1
−40°C to +85°C 3.3 8-Lead MSOP RM-8 L20
ADP3333ARMZ-3.3-RL
1
−40°C to +85°C 3.3 8-Lead MSOP RM-8 L20
ADP3333ARMZ-5-R7
1
−40°C to +85°C 5.0 8-Lead MSOP RM-8 L21
ADP3333ARMZ-5-RL
1
−40°C to +85°C 5.0 8-Lead MSOP RM-8 L21
1
Z = RoHS Compliant Part.

ADP3333ARMZ-2.77R7

Mfr. #:
Manufacturer:
Description:
Linear Voltage Regulators Hi Acc Ultralow 300mA LDO
Lifecycle:
New from this manufacturer.
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