LTC3785
16
3785fc
applicaTions inForMaTion
Determine the Proper Inductor Type Selection
The highest inductor current is during boost mode and
is given by:
I
L(MAX _ AV)
=
V
OUT
I
OUT
V
IN
η
where η = estimated efficiency in this mode (use 80%).
I
L(MAX _ AV)
=
3.3 3
2.7 0.8
= 4.6A
To limit the maximum efficiency loss of the inductor ESR
to below 5% the equation is:
ESR
L(MAX)
~
V
OUT
I
OUT
%Loss
I
L(MAX _ AV)
2
100
= 24mΩ
A suitable inductor for this application could be a Coiltron-
ics CD1-3R8 which has a rating DC current of 6A and ESR
of 13mΩ.
Choose a Proper MOSFET Switch
Using the same guidelines for ESR of the inductor, one
suitable MOSFET could be the Siliconix Si7940DP which
is a dual MOSFET in a surface mount package with 25mΩ
at 2.5V and a total gate charge of 12nC.
Checking the power dissipation of each switch will ensure
reliable operation since the thermal resistance of the
package is 60°C/W.
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
of T
J
= 100°C with ρ
100C
= 1.3, the power dissipation at
V
IN
= 2.7, and using the equations from the Efficiency
Considerations section:
PA(BOOST)=
3.3
2.7
3
2
1.3 0.025 = 0.43W
PC(BOOST)=
3.3 2.7
( )
3.3
2.7
2
3
2
1.3 0.025
+ 1• 3.3
3
3
2.7
0.45 9 500 10
3
= 0.09W
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
PB(BUCK)=
10 3.3
10
3
2
1.3 0.025 = 0.20W
PD(BOOST)=
3.3
10
3
2
1.3 0.025 = 0.10W
Now to double check the T
J
of the package with 50°C
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst-case. For applications
where the MOSFETs are in separate packages each device’s
maximum T
J
would have to be calculated.
T
J(PKG1)
= T
A
+ θ
JA
(PA + PB)
= 50 + 60 • (0.43 + 0.20) = 88°C
T
J(PKG2)
= T
A
+ θ
JA
(PC + PD)
= 50 + 60 • (0.09 + 0.10) = 60°C
Set The Maximum Current Limit
The equation for setting the maximum current limit of the
IC is given by:
R
ILSET
=
6000
R
DS(ON)A
I
LIMIT
Ω
The maximum current is set 25% above I
L(PEAK)
to account
for worst-case variation at 100°C = 6A.
R
ILSET
=
6000
0.025 6
= 42k
Choose the Input and Output Capacitance
The input capacitance should filter current ripple which is
worst-case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10mΩ or less will yield an
input ripple of 60mV.
The output capacitance should filter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
LTC3785
17
3785fc
applicaTions inForMaTion
PC BOARD LAYOUT CHECKLIST
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Place C
IN
, switch A, switch B and D1 in one compact
area. Place C
OUT
, switch C, switch D and D2 in one
compact area.
U
se immediate vias to connect the components (includ-
ing the LTC3785’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
F
lood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(V
IN
or GND). When laying out the printed circuit board,
the following checklist should be used to ensure proper
operation of the LTC3785.
S
egregate the signal and power grounds. All small-signal
components should return to the GND pin at one point.
The sources of switch B and switch C should also con-
nect to one point at the GND of the IC.
Place
switch B and switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
Keep the high dV/dT SW1, SW2, V
BST1
, V
BST2
, TG1 and
TG2 nodes away from sensitive small-signal nodes.
The
path formed by switch A, switch B, D1 and the C
IN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
C
OUT
capacitor also should have short leads and PC
trace lengths.
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
Connect the V
CC
decoupling capacitor C
VCC
closely to
the V
CC
and PGND pins.
Connect the top driver boost capacitor C
A
closely to
the V
BST1
and SW1 pins. Connect the top driver boost
capacitor C
B
closely to the V
BST2
and SW2 pins.
Connect the input capacitors C
IN
and output capaci-
tors C
OUT
close to the power MOSFETs. These capaci-
tors carry the MOSFET AC current in boost and buck
mode.
Connect
FB and V
SENSE
pin resistive dividers to the (+)
terminals of C
OUT
and signal ground. If a small V
SENSE
decoupling capacitor is used, it should be as close as
possible to the LTC3785 GND pin.
Route
I
SVIN
and I
SSW1
leads together with minimum PC
trace spacing. Ensure accurate current sensing with Kel-
vin connections across MOSFET A or sense resistor.
Route
I
SVOUT
and I
SSW2
leads together with minimum
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET D or sense
resistor.
Connect the feedback network close to IC, between the
V
C
and FB pins.
LTC3785
18
3785fc
package DescripTion
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
Typical applicaTion
V
CC
I
SVIN
TG1V
SENSE
BG1FB
V
C
TG2
BG2
SW2
3785 TA02
V
BST1
SW1
I
SSW1
I
SVOUT
RT
V
DRV
I
SSW2
V
BST2
CCM
I
LSET
MODE
RUN/SS
V
IN
1nF
1nF
205k
270pF
1.3k
R1
205k
12k
R2
121k
R
T
59k
R
ILSET
42.2k
121k
LTC3785
GND
C
VCC
4.7µF
Li-Ion
2.7V TO 4.2V
MA = MB = MC = MD = 1/2 Si7940DY
L1 = WÜRTH ELECTRONICS 744311470
D1 = D2 = PMEG2020EJ
9V REGULATED
WALL ADAPTER
V
IN
2.7V TO 10V
V
OUT
3.3V
3A
C
IN
22µF
MA
MB
D1
D2
OPTIONAL
OPTIONAL
MD
MC
C
A
0.22µF
C
B
0.22µF
CMDSH-3
CMDSH-3
L1
4.7µH
C
OUT
100µF
+
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2423
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER

LTC3785IUF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Efficiency, Synchronous, No Rsense, 4-Switch Buck-Boost Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union