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IRLR4343-701PBF

P1-P3P4-P6P7-P9P10-P11
4 www.irf.com
IRLR/U4343 & IRLU4343-701
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 10. Threshold Voltage vs. Temperature
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
V
SD
, Source-to-Drain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
I
S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
T
J
= 25°C
T
J
= 175°C
V
GS
= 0V
0 1 10 100 1000
V
DS
, Drain-toSource Voltage (V)
1
10
100
1000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R
DS
(on)
100µsec
25 50 75 100 125 150 175
T
J
, Junction Temperature (°C)
0
5
10
15
20
25
30
I
D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
-75 -50 -25 0 25 50 75 100 125 150 175
T
J
, Temperature ( °C )
0.5
1.0
1.5
2.0
V
G
S
(
t
h
)
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
I
D
= 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1
t
1
, Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
1.359 0.00135
0.5409 0.003643
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
R
1
R
1
R
2
R
2
τ
τ
C
Ci i/Ri
Ci= τi/Ri
www.irf.com 5
IRLR/U4343 & IRLU4343-701
Fig 13. Maximum Avalanche Energy Vs. Drain Current
Fig 12. On-Resistance Vs. Gate Voltage
Fig 14. Typical Avalanche Current Vs.Pulsewidth
Fig 15. Maximum Avalanche Energy Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
jmax
. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
4. P
D (ave)
= Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
av
= Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
T
jmax
(assumed as 25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see figure 11)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) = DT/ Z
thJC
I
av
=
2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
25 50 75 100 125 150 175
Starting T
J
, Junction Temperature (°C)
0
100
200
300
400
500
600
700
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
I
D
TOP
2.4A
3.3A
BOTTOM
19A
2.0 4.0 6.0 8.0 10.0
V
GS
, Gate-to-Source Voltage (V)
0
50
100
150
200
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
m
Ω
)
T
J
= 25°C
T
J
= 125°C
I
D
= 19A
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02
tav (sec)
0.1
1
10
100
1000
A
v
a
l
a
n
c
h
e
C
u
r
r
e
n
t
(
A
)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starting T
J
, Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
E
A
R
,
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
TOP Single Pulse
BOTTOM 1% Duty Cycle
I
D
= 19A
6 www.irf.com
IRLR/U4343 & IRLU4343-701
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
Fig 17b. Unclamped Inductive Waveforms
Fig 17a. Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
A
15V
20V
V
GS
Fig 19a. Gate Charge Test Circuit
Fig 19b Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2 Qgd Qgodr
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor
Current
1K
VCC
DUT
0
L
P1-P3P4-P6P7-P9P10-P11

IRLR4343-701PBF

Mfr. #:
Buy IRLR4343-701PBF
Manufacturer:
Infineon Technologies
Description:
MOSFET N-CH 55V 26A DPAK
Lifecycle:
New from this manufacturer.
Delivery:
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