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Figure 5. Configuration for OR/NOR Function
Table 4. OR/NOR TRUTH TABLE**
0
0
1
1
D0
1
1
1
1
D1
b
0
1
0
1
SEL
or b
0
1
1
1
Q
Q
SEL
VTD0
Q
SEL
VTD0
50 W
50 W
VTD1
VTD1
50 W
50 W
50 W
50 W
VTSEL
V
CC
VT or V
BB
b
D0
D0
D1
D1
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
Q
SEL
VTD0
Q
SEL
VTD0
50 W
50 W
VTD1
VTD1
50 W
50 W
50 W
50 W
VTSEL
b
D0
D0
D1
D1
Figure 6. Configuration for XOR/XNOR Function
1
0
0
D1
0
1
0
1
SEL
XOR b
0
1
1
0
Q
Table 5. XOR/XNOR TRUTH TABLE**
0
0
1
1
D0
1
b
** D0, D1, SEL are inverse of D0, D1, SEL unless specified oth‐
erwise.
D0
Q
SEL
VTD0
Q
SEL
VTD0
50 W
50 W
D0
D1
VTD1
VTD1
50 W
50 W
D1
50 W
50 W
VTSEL
Figure 7. Configuration for 2:1 MUX Function
D1
D0
Q
Table 6. 2:1 MUX TRUTH TABLE**
1
0
SEL
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
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Table 7. Interfacing Options
INTERFACING OPTIONS CONNECTIONS
CML Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to V
CC
LVDS Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open.
AC-COUPLED Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
Table 8. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistors (R
1
)
75 kW
Internal Input Pullup Resistor (R
2
)
37.5 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1 KV
> 50 V
> 4 KV
Moisture Sensitivity (Note 6) Pb Pkg Pb-Free Pkg
FCBGA-16, FCLGA-16
16-QFN
Level 3
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in
Transistor Count 364
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS (Note 7)
Symbol Parameter Condition 1 Condition 2 Rating Units
V
CC
Positive Power Supply V
EE
= 0 V 3.6 V
V
EE
Negative Power Supply V
CC
= 0 V -3.6 V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage |D
n
- D
n
| V
CC
- V
EE
w 2.8 V
V
CC
- V
EE
< 2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
mA
I
out
Output Current Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range 16-FCBGA, FCLGA
16-QFN
-40 to +70
-40 to +85
°C
°C
T
stg
Storage Temperature Range -65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 8)
0 lfpm
500 lfpm
0 lfpm
500 lfpm
16 FCBGA, FCLGA
16 FCBGA, FCLGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
q
JC
Thermal Resistance (Junction-to-Case) 2S2P (Note 8)
2S2P (Note 9)
16 FCBGA, FCLGA
16 QFN
5.0
4.0
°C/W
°C/W
T
sol
Wave Solder Pb (BGA)
Pb-Free
< 15 sec
< 3 sec @ 260°C
225
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
7. Maximum Ratings are those values beyond which device damage may occur.
8. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
9. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 10. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT V
CC
= 2.5 V; V
EE
= 0 V (Note 10)
Symbol Characteristic
-40°C 25°C 70°C(LGA)/85°C(QFN)**
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Negative Power Supply Current 23 30 39 23 30 39 23 30 39 mA
V
OH
Output HIGH Voltage (Note 11) 1460 1510 1560 1490 1540 1590 1515 1565 1615 mV
V
OL
Output LOW Voltage (Note 11)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1385
1015
1585
1215
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1445
1080
1640
1275
mV
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 13) D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Note 14) D, D
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
1.2 2.5 1.2 2.5 1.2 2.5 V
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
W
I
IH
Input HIGH Current (@V
IH
)D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
mA
I
IL
Input LOW Current (@V
IL
)D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
mA
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10.Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to -0.965 V.
11. All loading with 50 W to V
CC
- 2.0 V.
12.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
13.V
IH
cannot exceed V
CC
.
14.V
IL
always w V
EE
.
*Typicals used for testing purposes.
**The device packaged in FCLGA-16 have maximum ambient temperature specification of 70°C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85°C.

NBSG86AMNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2.5V/3.3V SiGe Diff Smart Gate
Lifecycle:
New from this manufacturer.
Delivery:
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