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IDT79RC32V364-100DA

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
Logic Diagram
Logic DiagramLogic Diagram
Logic Diagram
Figure 2 illustrates the direction and functional groupings for the processor signals of the RC32364.
Figure 2 Logic Diagram for RC32364
AD(31:4)
ALE
ADS*
Width(1:0)
BE(3:0)*
CIP*
MasterClk
ColdReset*
Reset*
V
CC
P
V
SS
P
Initialization
Interrupt
RC32364
Logic
Symbol
28
6
Interface
AD(3:0)
Addr(3:2)
4
I/D*
Rd*
Wr*
DataEn*
DT/R*
Ack*
Last*
2
NMI*
Int*(5:0)
DMA
Interface
BusReq*
BusGnt*
TCK
TDI/DINT*
TMS
TRST*
DCLK
PCST(2:0)
PCST(4:3)
DebugBoot
TDO/TPC
Bus Err*
Retry*
Handshake
Signals
4
2
3
2
Interface
Debug Emulator
Interface
Clock/Control Interface
System Interface
Vcc I/O
Vcc Core
Vss
11 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
RC32364 144-pin TQFP Package Pin-Out
RC32364 144-pin TQFP Package Pin-Out RC32364 144-pin TQFP Package Pin-Out
RC32364 144-pin TQFP Package Pin-Out
Note that the asterisk (*) identifies an active-low pin. For maximum flexibility and future design compatibility, N.C. pins should be left floating.
Pin Function Pin Function Pin Function Pin Function
1 Vcc I/O 37 NC 73 NC 109 NC
2 Vss 38 NC 74 NC 110 CIP*
3 TRST* 39 NC 75 NC 111 AD28
4 TDO/TPC* 40 NC 76 ADS* 112 Vss
5 TMS 41 Addr3 77 AD16 113 Vcc I/O
6 Vcc I/O 42 Vcc I/O 78 Vss 114 AD3
7 Vss 43 Vss 79 Vcc I/O 115 AD27
8 TCK 44 AD10 80 AD15 116 DataEn*
9 TDI/DINT* 45 ADDR2 81 I/D* 117 AD4
10 DebugBoot 46 BusReq* 82 VssP 118 Vss
11 PCST4 47 AD11 83 VccP 119 Vcc I/O
12 Vcc Core 48 Vcc I/O 84 NC 120 AD26
13 Vss 49 Vss 85 NC 121 AD5
14 PCST3 50 AD20 86 NC 122 DT/R*
15 NMI* 51 BE3 87 NC 123 AD25
16 INT0* 52 ColdReset* 88 MasterClk 124 Vss
17 PCST2 53 BusGNT* 89 Vss 125 Vcc Core
18 Vcc I/O 54 AD12 90 Vcc I/O 126 AD6
19 Vss 55 Vcc Core 91 AD31 127 AD24
20 DClk 56 Vss 92 AD0 128 AD7
21 INT1* 57 AD19 93 Ack* 129 AD23
22 Vcc Core 58 BE2 94 ALE 130 Vss
23 INT2* 59 Width1 95 Vss 131 Vcc I/O
24 Reset* 60 AD13 96 Vcc Core 132 AD8
25 Vcc Core 61 Vcc I/O 97 AD30 133 Vss
26 Vss 62 Vss 98 AD1 134 AD22
27 Wr* 63 AD18 99 Vcc Core 135 AD9
28 Rd* 64 BE1 100 BusErr* 136 Vss
29 PCST1 65 Width0 101 Retry* 137 Vcc I/O
30 INT3* 66 AD14 102 AD29 138 AD21
31 Vcc I/O 67 Vcc I/O 103 Vss 139 NC
32 Vss 68 Vss 104 Vcc I/O 140 NC
33 INT4* 69 AD17 105 AD2 141 NC
34 PCST0 70 BE0 106 Last* 142 Vss
35 INT5* 71 NC 107 NC 143 NC
36 NC 72 NC 108 NC 144 NC
12 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
Absolute Maximum Ratings
Absolute Maximum RatingsAbsolute Maximum Ratings
Absolute Maximum Ratings
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operation Temperature and Supply Voltag
Recommended Operation Temperature and Supply VoltagRecommended Operation Temperature and Supply Voltag
Recommended Operation Temperature and Supply Voltage
ee
e
A
AA
AC Electrical Characteristics — Commercial/Industrial Temperature
C Electrical Characteristics — Commercial/Industrial Temperature C Electrical Characteristics — Commercial/Industrial Temperature
C Electrical Characteristics — Commercial/Industrial Temperature
Ranges—RC32364
Ranges—RC32364Ranges—RC32364
Ranges—RC32364
V
CC
Core & V
CC
I/O = 3.3V ± 5%; T
Case
= 0°C to +85°C Commercial, T
Case
= -40° C to +85°C Industrial
Clock Parameters—RC32364
Clock Parameters—RC32364Clock Parameters—RC32364
Clock Parameters—RC32364
Note: Operation of the RC32364 is only guaranteed with the Phase Lock Loop enabled
Symbol Rating
RC32364
3.3V±5%
RC32364
3.3V±5%
Unit
Commercial Industrial
V
TERM
Terminal Voltage with respect to GND –0.5
1
to 4.0
1.
V
IN
minimum = –2.0V for pulse width less than 15ns. V
IN
should not exceed V
CC
+0.5 Volts.
–0.5
1
to 4.0 V
T
C
Operating Temperature(case) 0 to +85 -40 to +85 °C
T
BIAS
Case Temperature Under Bias –55 to +125 –55 to +125 °C
T
STG
Storage Temperature –55 to +125 –55 to +125 °C
I
IN
DC Input Current 20
2
2.
When V
IN
< 0V or V
IN
> V
CC
20
2
mA
I
OUT
DC Output Current 50
3
3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
50
3
mA
Grade Temperature Gnd
RC32364
V
CC Core & Vcc I/O
Commercial 0°C to +85°C (Case) 0V 3.3V±5%
Industrial -40°C + 85°C (Case) 0V 3.3V±5%
Parameter Symbol
Test
Conditions
RC32364 100MHz RC32364 133MHz
Units
Min Max Min Max
Pipeline clock frequency PClk 80 100 80 133 MHz
MasterClock HIGH t
MCHIGH
Transition ≤ 2ns6 —5 —ns
MasterClock LOW t
MCLOW
Transition ≤ 2ns6 —5 —ns
MasterClock Frequency
—
— 10501067MHz
MasterClock Period t
MCP
— 20 100 15 100 ns
Clock Jitter for MasterClock
1
1.
Guaranteed by design
t
JitterIn
1
——±250 — ±250 ps
MasterClock Rise Time
2
2.
Rise and Fall times are measured between 10% and 90%.
t
MCRise
— —3—3ns
MasterClock Fall Time
2
t
MCFall
— —3—3ns
JTAG Clock Period t
TCK
— 100 — 100 — ns
JTAG Clock High and Low Time t
TCKLOW,
t
TCKHIGH
—40—40—ns
JTAG Clock Fall and Rise Time t
TCKFall,
t
TCKRise
— —3—3ns
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IDT79RC32V364-100DA

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IC MPU MIPS32 100MHZ 144TQFP
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