18 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
Table 4 shows the pin numbering for the Standard EJTAG (EJT) connector. All the even numbered pins are connected to GROUND. The two right-
hand most columns show the target signal direction and the recommended termination at the target. Target termination resistors may be internal to the
chip or external on the board.
PIN SIGNAL
TARGET
I/O
TERMINATION
1
1.
The value of the series resistor may depend on the actual PCB layout situation.
1 TRST* (optional) Input 10 kΩ pull-down resistor
3 TDI/DINT* Input 10 kΩ pull-up resistor
5 TDO/TPC Output 33 Ω series resistor
7 TMS Input 10 kΩ pull-up resistor
9 TCK Input 10 kΩ pull-up resistor
2
2.
TCK pull-up resistor is not required according to the JTAG (IEEE1149) standard. It is indicated here to prevent a floating
CMOS input when the EJTAG connector is unconnected.
11 RST* Input 10 kΩ pull-up resistor
13 PCST[0] Output 33 Ω series
15 PCST[1] Output 33 Ω series
17 PCST[2] Output 33 Ω series
19 DCLK Output 33 Ω series
21 Debugboot Input 10 kΩ pull-down resistor
23 VIO Input Must be connected to the VCC IO supply of the device.
Table 4 Pin Numbering of the JTAG and EJTAG Target Connector
