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IDT79RC32V364-100DAG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
7 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
Width(1:0) O Bus Width
Indicates the Physical Memory/IO data bus size as follows:
BE*(3:0) O ByteEnables(3:0)/Addr(1:0)
Indicates which byte lanes are expected to participate in the transfer.
CIP* O Cycle-in-progress
Denotes that a cycle is in progress. Asserted in the address phase and continue asserted until the ACK* for the last data is sampled.
I/D* O I/D*
Indicates that the current cycle is for an instruction (active high) or data (active low) transaction.
Rd* O Read
This active-low signal indicates that the current transaction is a read.
Wr* O Write
This active-low signal indicates that the current cycle transaction is a write.
DataEn* O Data Enable
This active-low signal indicates that the AD bus is in data cycle. DEN* is asserted after the address cycle (starting of data cycle), and
deasserted at the end of the last data cycle.
DT/R* O Data Transmit/Receive
This active-low signal indicates the current cycle transaction of data direction. “High” is for a write cycle and “Low” is for a read cycle.
Ack* I Acknowledge Receiving Data
On read transactions, this signal indicates to the RC32364 that the memory system has placed valid data on the A/D bus, and that
the processor may move the data into the on-chip Read Buffer. On a write transaction, this indicates to the RC32364 that the mem-
ory system has accepted the data on the A/D bus.
Last* O Last Data
This active-low output is used to indicate the last data phase of a transfer.
Handshake Interface
BusErr* I Bus Error
Indicates that a bus error has occurred.
Pin Type Description
Table 3 System Interface Pin Descriptions (Page 2 of 4)
Width(1) Width(0)
Port
Width
0 0 8 bits
0 1 16 bits
1 0 32 bits
11Reserved
Byte Lanes Enabled In Data Transfer
Port Width BE(3) BE(2) BE(1) BE(0)
32-bit Used Used Used Used
16-bit Byte High
Enable
Not Used Address Bit 1
(A1)
Byte Low
Enable
8-bit Not Used
(Driven High)
Not Used
(Driven High)
Address Bit 1
(A1)
Address Bit 0
(A0)
8 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
Retry* I Retry
Indicates that the current bus cycle must be terminated. Retry* is ignored after acceptance of the first data during a read cycle. Dur-
ing a write, Retry* is recognized in all data cycles.
Initialization Interface
ColdReset* I ColdReset
This active-low signal is used for power-on reset.
Reset* I Reset
This active-low signal is used for both power-on and warm reset.
DMA Interface
BusReq* I Bus Request
This active-low signal is an input to the processor that is used to request mastership of the external interface bus. Mastership is
granted according to the assertion of this input, taken back based on its negation.
BusGnt* I/O Bus Grant/ModeBit(5)
This active-low signal is an output from the processor and is used to indicate that the CPU has relinquished mastership of the exter-
nal interface bus. BusGnt* goes low initially for at least 2 clocks to indicate that the CPU has relinquished mastership of the external
interface bus. After going low, BusGnt* returns high, either when the CPU makes an internal request for the bus or after BusReq* is
de-asserted.During the power-on reset (Cold Reset), BusGnt* is an input, ModeBit(5).
Interrupt Interface
NMI* I Non-Maskable Interrupt
NMI is falling edge sensitive and an asynchronous signal.
Int*(5:0) I Interrupt/ModeBit(9:6)
These interrupt inputs are active low to the CPU. During power-on, Int*(3:0) serves as ModeBit(9:6).
Debug Emulator Interface
TCK I Testclock
An input test clock, used to shift into or out of the Boundary-Scan register cells. TCK is independent of the system and the processor
clock with nominal 50% duty cycle.
TDI/DINT* I TDI/DINT*
On the rising edge of TCK, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller
state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit
back to Run Time Mode (standard JTAG). Requires an external pull-up on the board.
TDO/TPC O TDO/TPC
The TDO is serial data shifted out from instruction or data register on the falling edge of TCK. When no data is shifted out, the TDO
is tri-stated. During Real Time Mode, this signal provides a non-sequential program counter at the processor clock or at a division of
processor clock.
TMS I TMS
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising
edge of the TCK. Requires an external pull-up on the board.
TRST* I TRST*
The TRST* pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. Requires an
external pull-down on the board.
DCLK O DCLK
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the TDO signal at the processor clock
speed or any division of the internal pipeline.
Pin Type Description
Table 3 System Interface Pin Descriptions (Page 3 of 4)
9 of 21 June 20, 2000
79RC32364™
*Notice: The information in this document is subject to change without notice
PCST(2:0) I/O PCST(2:0)/ModeBit(2:0)
PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
During power-on reset (cold reset), PCST(2:0) serves as ModeBit(2:0).
PCST(4:3) I/O PCST(4:3)/ModeBit(4:3)
PC Trace Status Information. Reserved Pins for future expansion. During power-on reset, PCST(4:3) serves as ModeBit(4:3).
DebugBoot I DebugBoot
The Debug Boot input is used during reset and forces the CPU core to take a debug exception at the end of the reset sequence
instead of a reset exception. This enables the CPU to boot from the ICE probe without having the external memory working. This
input signal is level sensitive and is not latched internally. This signal will also set the JtagBrk bit in the JTAG_Control_Register[12].
Clock/Control Interface
MasterClk I MasterClock
This input clock is the bus clock. The core frequency is derived by multiplying this clock up.
VccP I VccP
Quiet Vcc for PLL.
VssP I VssP
Quiet Vss for PLL.
Vcc I/O I Supply voltage for output buffers.
Vcc Core I Supply voltage for internal logic.
Vss I Ground.
Pin Type Description
Table 3 System Interface Pin Descriptions (Page 4 of 4)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDT79RC32V364-100DAG

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IC MPU MIPS32 100MHZ 144TQFP
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