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AD1671JP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD1671
REV. B
–9–
Table I is a list of grounding and decoupling rules that should
be reviewed before laying out a printed circuit board.
Table I. Grounding and Decoupling Guidelines
Power Supply
Decoupling Comment
Capacitor Values 0.1 µF (Ceramic) and 1 µF
(Tantalum) Surface Mount Chip
Capacitors Recommended to
Reduce Lead Inductance
Capacitor Locations Directly at Positive and Negative
Supply Pins to Common Ground
Plane
Reference (REF OUT)
Capacitor Value 1 µF (Tantalum) to ACOM
Grounding
Analog Ground Ground Plane or Wide Ground
Return Connected to the Analog
Power Supply
Reference Ground Critical Common Connections
(REF COM) Should be Star Connected to REF
COM (as Shown in Figure 8)
Digital Ground Ground Plane or Wide Ground
Return Connected to the Digital
Power Supply
Analog and Digital Ground Connected Together Once at the
AD1671
UNIPOLAR (0 V TO +5 V) CALIBRATION
The AD1671 is factory trimmed to minimize offset, gain and
linearity errors. In some applications the offset and gain errors
of the AD1671 need to be externally adjusted to zero. This is
accomplished by trimming the voltage at AIN2 (Pin 22). The
circuit in Figure 9 is recommended for calibrating offset and
gain errors of the AD1671 when configured in the 0 V to +5 V
input range. If the offset trim resistor R1 is used, it should be
trimmed as follows, although a different offset can be set for a
particular system requirement. This circuit will give approxi-
mately ±5 mV of offset trim range. Nominally the AD1671 is
intended to have a 1/2 LSB offset so that the exact analog input
for a given code will be in the middle of that code (halfway be-
tween the transitions to the codes above it and below it). Thus,
the first transition (from 0000 0000 0000 to 0000 0000 0001)
will occur for an input level of +1/2 LSB (0.61 mV for 5 V
range).
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (4.998 V for a 5 V range). Trim R2 to give
the last transition (1111 1111 1110 to 1111 1111 1111). This
circuit will give approximately ±0.5% FS of adjustment range.
R2
50Ω
GAIN
ADJ
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
1µF
50k
+5V
–5V
OFFSET
ADJ
R1
10k
25Ω
0 TO +5V
V
IN
Figure 9. Unipolar (0 V to +5 V) Calibration
BIPOLAR (65 V) CALIBRATION
The connections for the bipolar ±5 V input range is shown in
Figure 10.
R2
50Ω
GAIN
ADJ
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
1µF
50k
+5V
–5V
OFFSET
ADJ
R1
10k
25Ω
V
IN
–5V TO +5V
Figure 10. Bipolar (
±
5 V) Calibration
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963 V) is applied and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
AD1671
REV. B
–10–
UNIPOLAR (0 V TO +2.5 V) CALIBRATION
The connections for the 0 V to +2.5 V input range calibration is
shown in Figure 11. Figure 11 shows an example of how the
offset error can be trimmed in front of the AD1671. The proce-
dure for trimming the offset and gain errors is the same as for
the unipolar 5 V range.
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
OFFSET ADJ
+15V
1k
0 TO +2.5V
V
IN
10k
10k
R2
2k
GAIN
ADJ
1µF
R1
AD845
1kΩ
390Ω
Figure 11. Unipolar (0 V to +2.5 V) Calibration
BIPOLAR (62.5 V) CALIBRATION
The connections for the bipolar ±2.5 V input range is shown in
Figure 12.
AIN1
AIN2
5k
5k
SHA OUT
BPO/UPO
AD1671
REF IN
REF OUT
SHA
OFFSET ADJ
+15V
1k
V
IN
10k
10k
R2
2k
GAIN
ADJ
1µF
R1
AD845
1kΩ
390Ω
–2.5V TO +2.5V
Figure 12. Bipolar (
±
2.5 V) Calibration
OUTPUT LATCHES
Figure 13 shows the AD1671 connected to the 74HC574 octal
D-type edge-triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum setup and
hold times of the 574 type latch must be less than 20 ns (t
DD
and t
SS
minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are S, AS, ALS, F or
BCT. New data from the AD1671 is latched on the rising edge
of the DAV (Pin 16) output pulse. Previous data can be latched
by inverting the DAV output with a 7404 type inverter.
Figure 13. AD1671 to Output Latches
OUT OF RANGE
An out-of-range condition exists when the analog input voltage
is beyond the input range (0 V to +2.5 V, 0 V to +5 V, ±2.5 V,
±5 V) of the converter OTR (Pin 15) is set low when the analog
input voltage is within the analog input range. OTR is set HIGH
and will remain HIGH when the analog input voltage exceeds
the input range by typically 1/2 LSB (OTR transition is tested to
±6 LSBs of accuracy) from the center of the ±full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement, overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 14. Sys-
tems requiring programmable gain conditioning prior to the
AD1671 can immediately detect an out-of-range condition, thus
eliminating gain selection iterations.
Table II. Out-of-Range Truth Table
OTR MSB Analog Input Is
0 0 In Range
0 1 In Range
1 0 Underrange
1 1 Overrange
MSB
OTR
MSB
OVER = "1"
UNDER = "1"
Figure 14. Overrange or Underrange Logic
AD1671
REV. B
–11–
Table III. Output Data Format
Input Analog Digital
Range Coding Input
l
Output OTR
2
0 V to +2.5 V Straight Binary
≤
–0.0003 V 0000 0000 0000 1
0 V 0000 0000 0000 0
+2.5 V 1111 1111 1111 0
≥ +2.5003 V 1111 1111 1111 1
0 V to +5 V Straight Binary ≤ –0.0006 V 0000 0000 0000 1
0 V 0000 0000 0000 0
+5 V 1111 1111 1111 0
≥ +5.0006 V 1111 1111 1111 1
–2.5 V to +2.5 V Offset Binary ≤ –2.5006 V 0000 0000 0000 1
–2.5 V 0000 0000 0000 0
+2.5 V 1111 1111 1111 0
≥ +2.4994 V 1111 1111 1111 1
–5 V to +5 V Offset Binary ≤ –5.0012 V 0000 0000 0000 1
–5 V 0000 0000 0000 0
+5 V 1111 1111 1111 0
≥ +4.9988 V 1111 1111 1111 1
–2.5 V to +2.5 V Twos Complement ≤ –2.5006 V 1000 0000 0000 1
(Using
MSB) –2.5 V 1000 0000 0000 0
+2.5 V 0111 1111 1111 0
≥ +2.4994 V 0111 1111 1111 1
–5 V to +5 V Twos Complement ≤ –5.0012 V 1000 0000 0000 1
(Using
MSB) –5 V 1000 0000 0000 0
+5 V 0111 1111 1111 0
≥ +4.9988 V 0111 1111 1111 1
NOTES
1
Voltages listed are with offset and gain errors adjusted to zero.
2
Typical performance.
OUTPUT DATA FORMAT
The AD1671 provides both MSB and MSB outputs, delivering
data in positive true straight binary for unipolar input ranges
and positive true offset binary or twos complement for bipolar
input ranges. Straight binary coding is used for systems that ac-
cept positive-only signals. If straight binary coding is used with
bipolar input signals, a 0 V input would result in a binary output
of 2048. The application software would have to subtract 2048
to determine the true input voltage. Host registers typically per-
form math on signed integers and assume data is in that format.
Twos complement format minimizes software overhead which is
especially important in high speed data transfers, such as a
DMA operation. The CPU is not bogged down performing data
conversion steps, hence the total system throughput is increased.
OPTIONAL EXTERNAL REFERENCE
The AD1671 includes an onboard +2.5 V reference. The refer-
ence input pin (REF IN) can be connected to reference output
pin (REF OUT) or a standard external +2.5 V reference can be
selected to meet specific system requirements. Fast switching in-
put dependent currents are modulated at the reference input.
The reference input voltage can be held with the use of a capaci-
tor. To prevent the AD1671’s onboard reference from oscil-
lating when not connected to REF IN, REF OUT must be
connected to +5 V. It is possible to connect REF OUT to +5 V
due to its output circuit implementation which shuts down the
reference.
I
LOGIC
VS. CONVERSION RATE
Figure 15 is the typical logic supply current vs. conversion rate
for various capacitor loads on the digital outputs.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1M
CONVERSION RATE – Hz
mA
1k
10k 100k
CL = 50pF
CL = 30pF
CL = 0pF
Figure 15. I
LOGIC
vs. Conversion Rate for Various
Capacitive Loads on the Digital Outputs
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AD1671JP

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Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-BIT 125 MSPS
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