AD1671JP Datasheet AD1671KQ, AD1671JQ, AD1671JP | P7-P9

AD1671

REV. B

–6–

DEFINITIONS OF SPECIFICATIONS

INTEGRAL NONLINEARITY (INL)

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale.” The

point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span)

before the first code transition (all zeros to only the LSB on).

“Full-scale” is defined as a level 1 1/2 LSB beyond the last code

transition (to all ones). The deviation is measured from the low

side transition of each particular code to the true straight line.

DIFFERENTIAL LINEARITY ERROR (NO MISSING

CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from the ideal value. Thus every

code has a finite width. Guaranteed no missing codes to 11- or

12-bit resolution indicates that all 2048 and 4096 codes, respec-

tively, must be present over all operating ranges. No missing

codes to 11 bits (in the case of a 12-bit resolution ADC) also

means that no two consecutive codes are missing.

UNIPOLAR OFFSET

The first transition should occur at a level 1/2 LSB above analog

common. Unipolar offset is defined as the deviation of the ac-

tual from that point. This offset can be adjusted as discussed

later. The unipolar offset temperature coefficient specifies the

maximum change of the transition point over temperature, with

or without external adjustments.

BIPOLAR ZERO

In the bipolar mode the major carry transition (0111 1111 1111 to

1000 0000 0000) should occur for an analog value 1/2 LSB be-

low analog common. The bipolar offset error and temperature

coefficient specify the initial deviation and maximum change in

the error over temperature.

GAIN ERROR

The last transition (from 1111 1111 1110 to 1111 1111 1111)

should occur for an analog value 1 1/2 LSB below the nominal

full scale (4.9963 volts for 5.000 volts full scale). The gain error

is the deviation of the actual level at the last transition from the

ideal level. The gain error can be adjusted to zero as shown in

Figures 4 through 7.

TEMPERATURE COEFFICIENTS

The temperature coefficients for unipolar offset, bipolar zero

and gain error specify the maximum change from the initial

(+25°C) value to the value at T

MIN

or T

MAX

POWER SUPPLY REJECTION

One of the effects of power supply error on the performance of

the device will be a small change in gain. The specifications

show the maximum full-scale change from the initial value with

the supplies at the various limits.

DYNAMIC SPECIFICATIONS

SIGNAL-TO-NOISE PLUS DISTORTION (S/ N+D) RATIO

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components, including har-

monics but excluding dc. The value for S/N+D is expressed in

decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

ENOB is calculated from the expression (S/N+D) = 6.02N +

1.76 dB, where N is equal to the effective number of bits.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and is ex-

pressed as a percentage or in decibels.

INTERMODULATION DISTORTION (IMD)

With inputs consisting of sine waves at two frequencies, fa and

fb, any device with nonlinearities will create distortion products

of order (m + n), at sum and difference frequencies of mfa ±

nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are

those for which m or n is not equal to zero. For example, the

second order terms are (fa + fb) and (fa – fb), and the third or-

der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2fb – fa).

The IMD products are expressed as the decibel ratio of the rms

sum of the measured input signals to the rms sum of the distor-

tion terms. The two signals are of equal amplitude and the peak

value of their sum is –0.5 dB from full scale. The IMD products

are normalized to a 0 dB input signal.

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT

The peak spurious or peak harmonic component is the largest

spectral component, excluding the input signal and dc. This

value is expressed in decibels relative to the rms value of a full-

scale input signal.

APERTURE DELAY

Aperture delay is the difference between thc switch delay and

the analog delay of the SHA. This delay represents the point in

time, relative to the rising edge of ENCODE input, that the

analog input is sampled.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive

samples.

FULL POWER BANDWIDTH

The input frequency at which the amplitude of the recon-

structed fundamental is reduced by 3 dB for a full-scale input.

AD1671

REV. B

–7–

THEORY OF OPERATION

The AD1671 uses a successive subranging architecture. The

analog-to-digital conversion takes place in four independent

steps or flashes. The sampled analog input signal is subranged

to an intermediate residue voltage for the final 12-bit result by

utilizing multiple flashes with subtraction DACs (see the AD1671

functional block diagram).

The AD1671 can be configured to operate with unipolar (0 V to

+5 V, 0 V to +2.5 V) or bipolar (±5 V, ±2.5 V) inputs by con-

necting AIN (Pins 22, 23), SHA OUT (Pin 25) and BPO/UPO

(Pin 26) as shown in Figure 2.

–2.5V

+2.5V

AIN1

AIN2

SHA OUT

BPO/UPO

AD1671

REF IN

REF OUT

SHA

AIN1

AIN2

SHA OUT

BPO/UPO

AD1671

REF IN

REF OUT

+2.5V

SHA

a. 0 V to +2.5V Input Range b.

2.5 V Input Range

AIN1

AIN2

SHA OUT

BPO/UPO

AD1671

REF IN

REF OUT

±5V SHA

AIN1

AIN2

SHA OUT

BPO/UPO

AD1671

REF IN

REF OUT

+5V

SHA

c. 0 V to +5 V Input Range d.

5 V Input Range

Figure 2. AD1671 Input Range Connections

The AD1671 conversion cycle begins by simply providing an

active HIGH level on the ENCODE pin (Pin 17). The rising

edge of the ENCODE pulse starts the conversion. The falling

edge of the ENCODE pulse is specified to operate within a win-

dow of time, less than 50 ns after the rising edge of ENCODE

or after the falling edge of DAV. The time window prevents

digitally coupled noise from being introduced during the final

stages of conversion. An internal timing generator circuit accu-

rately controls SHA, flash and DAC timing.

Upon receipt of an ENCODE command the input voltage is

held by the front-end SHA and the first 3-bit flash converts the

analog input voltage. The 3-bit result is passed to a correction

logic register and a segmented current output DAC. The DAC

output is connected through a resistor (within the Range/Span

Select Block) to SHA OUT. A residue voltage is created by sub-

tracting the DAC output from SHA OUT, which is less than

one eighth of the full-scale analog input. The second flash has

an input range that is configured with one bit of overlap with the

previous DAC. The overlap allows for errors during the flash

conversion. The first residue voltage is connected to the second

3-bit flash and to the noninverting input of a high speed, differ-

ential, gain of eight amplifier. The second flash result is passed

to the correction logic register and to the second segmented cur-

rent output DAC. The output of the second DAC is connected

to the inverting input of the differential amplifier. The differen-

tial amplifier output is connected to a two-step, backend, 8-bit

flash. This 8-bit flash consists of coarse and fine flash convert-

ers. The result of the coarse 4-bit flash converter, also config-

ured to overlap one bit of DAC 2, is connected to the correction

logic register and selects one of 16 resistors from which the fine

4-bit flash will establish its span voltage. The fine 4-bit flash is

connected directly to the output latches.

The internal timing generator automatically places the SHA into

the acquire mode when DAV goes LOW. Upon completion of

conversion (when DAV is set HIGH), the SHA has acquired the

analog input to the specified level of accuracy and will remain in

the sample mode until the next ENCODE command.

The AD1671 will flag an out-of-range condition when the input

voltage exceeds the analog input range. OTR (Pin 15) is active

HIGH when an out-of-range high or low condition exists. Bits

1–12 are HIGH when the analog input voltage is greater than

the selected input range and LOW when the analog input is less

than the selected input range.

AD1671 DYNAMIC PERFORMANCE

The AD1671 is specified for dc and dynamic performance. A

sampling converter’s dynamic performance reflects both quan-

tizer and sample-and-hold amplifier (SHA) performance. Quan-

tizer nonlinearities, such as INL and DNL, can degrade dynamic

performance. However, a SHA is the critical element which has to

accurately sample fast slewing analog input signals. The AD1671’s

high performance, low noise, patented on-chip SHA minimizes

distortion and noise specifications. Nonlinearities are minimized

by using a fast slewing, low noise architecture and subregulation

of the sampling switch to provide constant offsets (therefore

reducing input signal dependent nonlinearities).

Figure 3 is a typical 2k point Fast Fourier Transform (FFT)

plot of a 100 kHz input signal sampled at 1 MHz. The funda-

mental amplitude is set at –0.5 dB to avoid input signal clipping

of offset or gain errors. Note the total harmonic distortion is ap-

proximately –81 dB, signal to noise plus distortion is 71 dB and

the spurious free dynamic range is 84 dB.

SIGNAL AMPLITUDE – dB

–100

–50

–75

–25

FREQUENCY

Figure 3. AD1671 FFT Plot, f

= 100 kHz, f

SAMPLE

= 1 MHz

AD1671

REV. B

–8–

–45–50

–5–10–15–20

–25

–30–35–40

ANALOG INPUT – dB

SPURIOUS FREE DYNAMIC RANGE – dB

Figure 7. Spurious Free Dynamic Range vs. Input

Amplitude, f

= 250 kHz

APPLYING THE AD1671

GROUNDING AND DECOUPLING RULES

Proper grounding and decoupling should be a primary design

objective in any high speed, high resolution system. The

AD1671 separates analog and digital grounds to optimize the

management of analog and digital ground currents in a system.

The AD1671 is designed to minimize the current flowing from

REF COM (Pin 20) by directing the majority of the current

from V

(+5 V–Pin 28) to V

(–5 V–Pin 1). Minimizing ana-

log ground currents hence reduces the potential for large ground

voltage drops. This can be especially true in systems that do not

utilize ground planes or wide ground runs. REF COM is also

configured to be code independent, therefore reducing input de-

pendent analog ground voltage drops and errors. Code depen-

dent ground current is diverted to ACOM (Pin 27). Also critical

in any high speed digital design is the use of proper digital

grounding techniques to avoid potential CMOS “ground

bounce.” Figure 3 is provided to assist in the proper layout,

grounding and decoupling techniques.

AIN1

REF IN

BPO/UPO

ACOM

BIT 1

BIT 12

DCOM

AD1671

ENCODE

DAV

OTR

MSB

AGP*

DGP*

+5V –5V

*GROUND PLANE RECOMMENDED

AIN2

REF OUT

SHA OUT

REF COM

1µF

LOGIC

V (±5V)

1 18

+5V

0.1µF

10µF

0.1µF10µF0.1µF10µF

Figure 8. AD1671 Grounding and Decoupling

Figure 4 plots both S/(N+D) and Effective Number of Bits

(ENOB) for a 100 kHz input signal sampled from 666 kHz to

1.25 MHz.

SAMPLING FREQUENCY – kHz

72.5

1250

68.5

70.5

714666

69.5

71.5

11111000909833769

S/(N+D) – dB

11.75

11.50

11.25

11.00

EFFECTIVE NUMBER OF BITS

Figure 4. S/(N/D) vs. Sampling Frequency, f

= 100 kHz

Figure 5 is a THD plot for a full-scale 100 kHz input signal with

the sample frequency swept from 666 kHz to 1.25 MHz.

–68

–86

1250

–84

–76

714666

–82

–80

–78

–74

–72

–70

11111000909833769

SAMPLING FREQUENCY – kHz

THD – dB

Figure 5. THD vs. Sampling Rate, f

= 100 kHz

The AD1671’s SFDR performance is ideal for use in communi-

cation systems such as high speed modems and digital radios.

The SFDR is better than 84 dB with sample rates up to 1.11 MHz

and increases as the input signal amplitude is attenuated by ap-

proximately 3 dB. Note also the SFDR is typically better than

80 dB with input signals attenuated by up to –7 dB.

1250714666 11111000909833769

SAMPLING FREQUENCY – kHz

SPURIOUS FREE DYNAMIC RANGE – dB

–86

–68

–84

–76

–82

–80

–78

–74

–72

–70

–88

–90

Figure 6. Spurious Free Dynamic Range vs. Sampling

Rate, f

= 100 kHz

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD1671JP

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Analog to Digital Converters - ADC 12-BIT 125 MSPS

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AD1671JP

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