AD569JNZ Datasheet AD569JPZ, AD569KPZ, AD569AD | P7-P9

AD569

REV. A

–6–

Figure 5. Typical DNL at Segment Boundary Transitions

a. Segment 1

b. Segment 256

Figure 6. Typical DNL Within Segments

MULTIPLYING FEEDTHROUGH ERROR: This is the error

due to capacitive feedthrough from the reference to the output

with the input registers loaded with all zeroes.

FULL-SCALE ERROR: The AD569’s voltage dividing archi-

tecture gives rise to a fixed full-scale error which is independent

of the reference voltage. This error is trimmed by adjusting the

voltage applied to the +V

REF

terminals.

DIGITAL-TO-ANALOG GLITCH IMPULSE: The charge in-

jected into the analog output when a new input is latched into

the DAC register gives rise to the Digital-to-Analog Glitch

Impulse.

Glitches can be due to either time skews between the input bits

or charge injection from the internal switches. Glitch Impulse

for the AD569 is mainly due to charge injection, and is mea-

sured with the reference connections tied to ground. It is speci-

fied as the area of the glitch in nV-secs.

TOTAL ERROR: The worst-case Total Error is the sum of the

fixed full-scale and offset errors and the linearity error.

POWER SUPPLY AND REFERENCE VOLTAGE RANGES

The AD569 is specified for operation with ±12 volt power

supplies. With ±10% power supply tolerances, the maximum

reference voltage range is ±5 volts. Reference voltages up to

±6 volts can be used but linearity will degrade if the supplies

approach their lower limits of ±10.8 volts (12 volts - 10%).

If ±12 volt power supplies are unavailable in the system, several

alternative schemes may be used to obtain the needed supply

voltages. For example, in a system with ±15 V supplies, a single

Zener diode can be used to reduce one of the supplies to 9 volts

with the remaining one left at 15 volts. Figure 7a illustrates this

scheme. A 1N753A or equivalent diode is an appropriate choice

for the task. Asymmetrical power supplies can be used since the

AD569’s output is referenced to –V

REF

only and thus floats

relative to logic ground (GND, Pin 18). Assuming a worst-case

±1.5 volt tolerance on both supplies (10% of 15 volts), the

maximum reference voltage ranges would be +6 and –2 volts for

= +15 V and V

= –9 V, and +2 to –8 volts for +V

= 9 V

and –V

= –15 V .

Alternately, two 3 V Zener diodes or voltage regulators can be

used to drop each ±15 volt supply to ±12 volts, respectively. In

Figure 7b, 1N746A diodes are a good choice for this task.

A third method may be used if both ±15 volt and ±5 volt sup-

plies are available. Figure 7c shows this approach. A combina-

tion of +V

= +15 V and –V

= –5 V can support a reference

range of 0 to 6 volts, while supplies of +V

= +5 V and –V

–15 V can support a reference range of 0 to –8 volts. Again,

10% power supply tolerances are assumed.

NOTE: Operation with +V

= +5 V alters the input latches’ op-

erating conditions causing minimum write pulse widths to ex-

tend to 1 µs or more. Control signals

CS, HBE, LBE, and

LDAC should, therefore, be tied low to render the latches trans-

parent.

No timing problems exist with operation at +V

= 9 V and

–V

= –15 V. However, 10% tolerances on these supplies gener-

ate a worst-case condition at –V

= –16.5 V and +V

= +7.5 V

(assuming +V

is derived from a +15 V supply). Under these

conditions, write pulse widths can stretch to 200 ns with similar

degradation of data setup and hold times. However, ±0.75 V

tolerances (±5%) yield minimal effects on digital timing with

write pulse widths remaining below 100 ns.

Finally, Figure 7d illustrates the use of the combination of an

AD588 and AD569 in a system with ±15 volt supplies. As

shown, the AD588 is connected to provide ±5 V to the refer-

ence inputs of the AD569. It is doing double-duty by simulta-

neously regulating the supply voltages for the AD569 through

the use of the level shifting Zeners and transistors. This scheme

utilizes the capability of the outputs of the AD588 to source as

well as sink current. Two other benefits are realized by using

this approach. The first is that the AD569 is no longer directly

connected to the system power supplies. Output sensitivity to

variations in those supplies is, therefore, eliminated. The second

AD569

REV. A

–7–

benefit is that, should a Zener diode fail (a short circuit would

be the most likely failure), the supply voltage decreases. This

differs from the situation where the diode is used as a series

regulator. In that case, a failure would place the unregulated

supply voltage on the AD569 terminal.

a. Zener Regulates Negative Supply

b. Diodes Regulate Both Supplies

c. Use of

15 V and

5 V Supplies

d. AD588 Produces References and Supply Voltages

Figure 7. Power Supply Options

ANALOG CIRCUIT CONNECTIONS

The AD569 is intended for use in applications where high reso-

lution and stability are critical. Designed as a multiplying D/A

converter, the AD569 may be used with a fixed dc reference or

an ac reference. V

REF

may be any voltage or combination of

voltages at +V

FORCE

and –V

FORCE

that remain within the bounds

set for reference voltages as discussed in the power supply range

section. Since the AD569 is a multiplying D/A converter, its

output voltage, V

OUT

, is proportional to the product of the digi-

tal input word and the voltage at the reference terminal. The

transfer function is V

OUT

= D·V

REF

where D is the fractional bi-

nary value of the digital word applied to the converter using

offset-binary coding. Therefore, the output will range from

–V

REF

for a digital input code of all zeros (0000

) to +V

REF

for

an input code of all ones (FFFF

For applications where absolute accuracy is not critical, the

simple reference connection in Figure 8 can be used. Using only

the reference force inputs, this configuration maintains linearity

and 16-bit monotonicity, but introduces small, fixed offset and

gain errors. These errors are due to the voltage drops across re-

sistors R

and R

shown in Figure 9. With a 10 V reference

voltage, the gain and offset errors will range from 80 mV to

100 mV. Resistors R

and R

were included in the first resistor

string to avoid degraded linearity due to uneven current densi-

ties at the string’s endpoints. Similarly, linearity would degrade

if the reference voltage were connected across the reference

sense terminals. Note that the resistance between the force and

sense terminals cannot be measured with an ohmmeter; the lay-

out of the thin-film resistor string adds approximately 4 kΩ of

resistance (R

) at the sense tap.

Figure 8. Simple Reference Connection

For those applications in which precision references and high

accuracy are critical, buffer amplifiers are used at +V

REF

and

–V

REF

as shown in Figure 10 to force the voltage across resistors

R1 to R256. This insures that any errors induced by currents

flowing through the resistances of the package pins, bond wires,

aluminum interconnections, as well as R

and R

are mini-

mized. Suitable amplifiers are the AD517, AD OP07, AD OP27,

or the dual amplifier, the AD712. Errors will arise, however, as

the buffer amplifiers’ bias currents flow through R

(4 kΩ). If

the bias currents produce such errors, resistance can be inserted

at the noninverting terminal (R

) of the buffer amplifiers to

compensate for the errors.

AD569

REV. A

–8–

Figure 9. MSB Resistor Divider

Figure 10. Reference Buffer Amplifier Connections

Figure 11. Ultralow Drift

5 V Tracking Reference

Figure 12. Low-Cost

5 V Reference

+5 V reference. A dual op amp, the AD712, buffers the refer-

ence input terminals preserving the absolute accuracy of the

AD569. The optional noise-reduction capacitor and gain

adjust trimmer allow further elimination of errors. The low-

cost AD584 offers 2.5 V, 5 V, 7.5 V, and 10 V options and

can be connected for ±5 V tracking outputs as shown in Figure

13. Again, an AD712 is used to buffer the reference input

terminals.

Figures 11, 12, and 13 show reference configurations for various

output ranges. As shown in Figure 11, the pin-programmable

AD588 can be connected to provides tracking ±5 V outputs

with 1-3ppm/°C temperature stability. Buffer amplifiers are in-

cluded for direct connection to the AD569. The optional gain

and balance adjust trimmers allow bipolar offset and full-scale

errors to be nulled. In Figure 12, the low-cost AD586 provides

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD569JNZ

Mfr. #:

Buy AD569JNZ

Manufacturer:

Description:

IC DAC 16BIT MONO 28-DIP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD569JNZ

AD569JNZ

Products related to this Datasheet