74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 August 2013 9 of 18
NXP Semiconductors
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
t
h
hold time DSA, and DSB to CP;
see Figure 9
V
CC
= 4.5 V +4 2- 4 - 4 - ns
f
max
maximum
frequency
for Cp, see Figure 7
V
CC
= 4.5 V 27 55 - 22 - 18 - MHz
V
CC
= 5.0 V; C
L
=15pF - 61 - - - - - MHz
C
PD
power
dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-40- - - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
(1) Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
001aal392
CP input
Qn
output
t
PHL
t
PLH
t
THL
t
TLH
t
W
V
OH
V
I
GND
V
OL
V
M
V
M
V
X
V
Y
1/f
max
Table 8. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC164-Q100 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT164-Q100 1.3 V 1.3 V 0.1V
CC
0.9V
CC
